參數(shù)資料
型號: TMS320VC5409ZGU-80
廠商: Texas Instruments
文件頁數(shù): 31/93頁
文件大?。?/td> 0K
描述: IC FIXED POINT DSP 144-BGA
標準包裝: 160
系列: TMS320C54x
類型: 定點
接口: 主機接口,McBSP
時鐘速率: 80MHz
非易失內(nèi)存: ROM(32 kB)
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 144-LFBGA
供應商設(shè)備封裝: 144-BGA MICROSTAR(12x12)
包裝: 托盤
配用: 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Functional Overview
37
April 1999 Revised October 2008
SPRS082F
This clock generator allows system designers to select the clock source. The sources that drive the clock
generator are:
A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins
of the 5409 to enable the internal oscillator.
An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left
unconnected.
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides
various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can
be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a
built-in software-programmable PLL can be configured in one of two clock modes:
PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved
using the PLL circuitry.
DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can
be completely disabled in order to minimize power dissipation.
The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode
register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Upon
reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the
CLKMD1 CLKMD3 pins as shown in Table 311.
Table 311. Clock Mode Settings at Reset
CLKMD1
CLKMD2
CLKMD3
CLKMD
RESET VALUE
CLOCK MODE
CLKMD1
CLKMD2
CLKMD3
RESET VALUE
CLOCK MODE
0
E007h
PLL x 15
0
1
9007h
PLL x 10
0
1
0
4007h
PLL x 5
1
0
1007h
PLL x 2
1
0
F007h
PLL x 1
1
0000h
1/2 (PLL disabled)
1
0
1
F000h
1/4 (PLL disabled)
0
1
Reserved
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