參數(shù)資料
型號(hào): TMS320VC5409ZGU-80
廠商: Texas Instruments
文件頁數(shù): 49/93頁
文件大?。?/td> 0K
描述: IC FIXED POINT DSP 144-BGA
標(biāo)準(zhǔn)包裝: 160
系列: TMS320C54x
類型: 定點(diǎn)
接口: 主機(jī)接口,McBSP
時(shí)鐘速率: 80MHz
非易失內(nèi)存: ROM(32 kB)
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 144-LFBGA
供應(yīng)商設(shè)備封裝: 144-BGA MICROSTAR(12x12)
包裝: 托盤
配用: 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Documentation Support
53
April 1999 Revised October 2008
SPRS082F
5.5
Divide-By-Two/Divide-By-Four Clock Option (PLL Disabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four
to generate the internal machine cycle. The selection of the clock mode is described in the clock generator
section.
When an external clock source is used, the frequency injected must conform to specifications listed in the
timing requirements table. Table 52 and Table 53 assumes testing over recommended operating conditions
and H = 0.5tc(CO) (see Figure 53).
Table 52.
Divide-By-Two/Divide-By-Four Clock Option (PLL Disabled) Timing Requirements
MIN
MAX
UNIT
tc(CI)
Cycle time, X2/CLKIN
20
ns
tf(CI)
Fall time, X2/CLKIN
8
ns
tr(CI)
Rise time, X2/CLKIN
8
ns
tw(CIL)
Pulse duration, X2/CLKIN low
5
ns
tw(CIH)
Pulse duration, X2/CLKIN high
5
ns
This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
Table 53.
Divide-By-Two/Divide-By-Four Clock Option (PLL Disabled) Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
tc(CO)
Cycle time, CLKOUT
40
2tc(CI)
ns
td(CIH-CO)
Delay time, X2/CLKIN high to CLKOUT high/low
4
10
17
ns
tf(CO)
Fall time, CLKOUT
2
ns
tr(CO)
Rise time, CLKOUT
2
ns
tw(COL)
Pulse duration, CLKOUT low
H2
H1
H
ns
tw(COH)
Pulse duration, CLKOUT high
H2
H1
H
ns
This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
tr(CO)
tf(CO)
CLKOUT
X2/CLKIN
tw(COL)
td(CIH-CO)
tf(CI)
tr(CI)
tc(CO)
tc(CI)
tw(COH)
tw(CIH)
tw(CIL)
Figure 53. External Divide-by-Two Clock Timing
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