Table 533 and Table 534 assume testing over reco" />
參數(shù)資料
型號(hào): TMS320VC5409ZGU-80
廠商: Texas Instruments
文件頁數(shù): 81/93頁
文件大?。?/td> 0K
描述: IC FIXED POINT DSP 144-BGA
標(biāo)準(zhǔn)包裝: 160
系列: TMS320C54x
類型: 定點(diǎn)
接口: 主機(jī)接口,McBSP
時(shí)鐘速率: 80MHz
非易失內(nèi)存: ROM(32 kB)
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 144-LFBGA
供應(yīng)商設(shè)備封裝: 144-BGA MICROSTAR(12x12)
包裝: 托盤
配用: 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Documentation Support
82
April 1999 Revised October 2008
SPRS082F
5.14.2
HPI16 Mode
Table 533 and Table 534 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 531 through Figure 532). In the following tables, DS refers to the logical OR of HCS, HDS1, and
HDS2, and HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). These timings are shown
assuming that HDS is the signal controlling the transfer. See the TMS320C54x DSP Reference Set, Volume
5: Enhanced Peripherals (literature number SPRU302) for additional information.
Table 533. HPI16 Mode Timing Requirements
MIN
MAX
UNIT
tsu(HBV-DSL)
Setup time, HAD valid before DS falling edge
5
ns
th(DSL-HBV)
Hold time, HAD valid after DS falling edge
5
ns
tsu(HAV-DSL)
Setup time, HAD valid before DS falling edge
4H+3
ns
th(DSH-HAV)
Hold time, address valid after DS rising edge
1
ns
tsu(HDV-DSH)
Setup time, Dx valid before DS high (HPI write)
3
ns
th(DSH-HDV)W
Hold time, Dx valid after DS high (HPI write)
2
ns
tw(DSL)
Pulse duration, DS low
20
ns
tw(DSH)
Pulse duration, DS high
10
ns
tc(DSH-DSH)
Cycle time, DS rising edge to next DS rising
edge
Nonmultiplexed mode (no increment)
with no DMA activity.
12H
ns
tc(DSH-DSH)
(Minimum timings represent WRITEs while
maximum timings represent READs)
Nonmultiplexed mode (no increment)
with 16-bit DMA activity.
20H
ns
DS refers to the logical OR of HCS and HDS1 and HDS2.
Dx refers to any of the HPI data bus pins (D0, D1, D2, etc.).
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