參數(shù)資料
型號(hào): TMS320VC5409ZGU-80
廠商: Texas Instruments
文件頁(yè)數(shù): 51/93頁(yè)
文件大?。?/td> 0K
描述: IC FIXED POINT DSP 144-BGA
標(biāo)準(zhǔn)包裝: 160
系列: TMS320C54x
類型: 定點(diǎn)
接口: 主機(jī)接口,McBSP
時(shí)鐘速率: 80MHz
非易失內(nèi)存: ROM(32 kB)
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 144-LFBGA
供應(yīng)商設(shè)備封裝: 144-BGA MICROSTAR(12x12)
包裝: 托盤(pán)
配用: 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Documentation Support
55
April 1999 Revised October 2008
SPRS082F
5.7
Memory and Parallel I/O Interface Timing
5.7.1 Memory Read
External memory reads can be performed in consecutive or nonconsecutive mode under control of the
CONSEC bit in the BSCR. Table 56 and Table 57 assume testing over recommended operating conditions
with MSTRB = 0 and H = 0.5tc(CO) (see Figure 55).
Table 56. Memory Read Timing Requirements
MIN
MAX
UNIT
ta(A)M
Access time, read data access from address valid
2H10
ns
ta(MSTRBL)
Access time, read data access from MSTRB low
2H10
ns
tsu(D)R
Setup time, read data before CLKOUT low
8
ns
th(D)R
Hold time, read data after CLKOUT low
0
ns
th(A-D)R
Hold time, read data after address invalid
0
ns
th(D)MSTRBH Hold time, read data after MSTRB high
1
ns
Address, PS, and DS timings are all included in timings referenced as address.
This access timing reflects a zero wait-state timing.
Table 57. Memory Read Switching Characteristics
PARAMETER
MIN
MAX
UNIT
td(CLKL-A)
Delay time, CLKOUT low to address valid§
0
3
ns
td(CLKH-A)
Delay time, CLKOUT high (transition) to address valid
0
3
ns
td(CLKL-MSL)
Delay time, CLKOUT low to MSTRB low
0
3
ns
td(CLKL-MSH)
Delay time, CLKOUT low to MSTRB high
0
3
ns
th(CLKL-A)R
Hold time, address valid after CLKOUT low§
0
3
ns
th(CLKH-A)R
Hold time, address valid after CLKOUT high
0
3
ns
Address, PS, and DS timings are all included in timings referenced as address.
§ In the case of a memory read preceded by a memory read
In the case of a memory read preceded by a memory write
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