參數(shù)資料
型號: TMX320F2810GHHS
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: DIGITAL SIGNAL PROCESSORS
中文描述: 數(shù)字信號處理器
文件頁數(shù): 24/103頁
文件大?。?/td> 1341K
代理商: TMX320F2810GHHS
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
APRIL 2001
REVISED SEPTEMBER 2001
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
device emulation registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical device
signals. The registers are defined in Table 7.
Table 7. Device Emulation Registers
NAME
ADDRESS RANGE
SIZE (x16)
DESCRIPTION
DEVICECNF
0x0000 0880
0x0000 0881
2
Device Configuration Register
DEVICEID
0x0000 0882
0x0000 0883
2
Device ID Register
PROTSTART
0x0000 0884
1
Block Protection Start Address Register
PROTRANGE
0x0000 0885
1
Block Protection Range Address Register
reserved
0x0000 0886
0x0000 09FF
378
Table 8. DEVICECNF Register Bit Definitions
BITS
NAME
TYPE
RESET
DECSRIPTION
1:0
reserved
R/W
1,1
For Test Only
2
reserved
R =0
0
3
VMAPS
R
0/1
VMAP Configure Status. This indicates the status of VMAP.
4
reserved
R = 0
0
5
XRS
R
0/1
Reset Input Signal Status. This is connected directly to the XRS input pin.
6
reserved
R = 1
1
7
reserved
R/W
0
14:8
reserved
R = 0
0:0
15
reserved
R/W
0
For Test Only
16
reserved
R = 1
1
17
reserved
R = 1
1
18
reserved
R = 1
1
19
ENPROT
R/W
1
Enable Write-Read Protection Mode Bit. This bit, when set to 1, will enable
write-read protection as specified by the PROTSTART and PROTRANGE
registers. This bit, when set to 0, disables this protection mode.
31:20
spares
R = 0
0
Table 9. DEVICEID Register Bit Definitions
BITS
NAME
TYPE
RESET
DECSRIPTION
15:0
PARTID
R
Dependent on
device
These 16 bits specify the part number of the device as follows:
0x0001:
F2810 device
0x0002:
F2812 device
31:16
REVID
R
0x0001
(for first silicon)
These 16 bits specify the silicon revision number for the particular
part. This number always starts with 0x0001 on the first revision of the
silicon and is incremented on any subsequent revisions.
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