參數(shù)資料
型號： TMX320F2810GHHS
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 27/103頁
文件大小： 1341K
代理商： TMX320F2810GHHS
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
27
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
external interface, XINTF (F2812 only)
This section gives a top-level view of the external interface (XINTF) that is implemented on the F2812 device.
The external interface is a non-multiplexed asynchronous bus, similar to the C240x external interface. The
external interface on the F2812 is mapped into five fixed zones shown in Figure 3.
Figure 3 shows the F2812 XINTF signals.
XD(15:0)
XA(18:0)
XZCS0
XZCS6
XZCS7
XZCS6AND7
XZCS1
XZCS2
XWE
XRNW
XREADY
XMP/MC
XHOLD
XHOLDA
XCLKOUT (see Note D)
XRD
XINTF Zone 0
(8K
×
16)
XINTF Zone 1
(8K
×
16)
XINTF Zone 6
(1M
×
16)
XINTF Zone 7
(16K
×
16)
(mapped here if MP/MC =1)
0x0040
–
0000
0x003F
–
C000
0x0020
–
0000
0x0010
–
0000
0x0000
–
6000
0x0000
–
4000
0x0000
–
2000
0x0000
–
0000
Data Space
Prog Space
XINTF Zone 2
(512K
×
16)
0x0008
–
0000
NOTES: A. The mapping of XINTF Zone 7 is dependent on the XMP/MC device input signal and the MP/MC mode bit (bit 8 of XINTCNF2
register). Zones 0, 1, 2, and 6 are always enabled.
B. Each zone can be programmed with different wait states, setup and hold timings, and is supported by zone chip selects (XZCS0,
XZCS1, XZCS2, XZCS6AND7), which toggle when an access to a particular zone is performed. These features enable glueless
connection to many external memories and peripherals.
C. The chip selects for Zone 6 and 7 are ANDed internally together to form one chip select (XZCS6AND7). Any external memory
that is connected to XZCS6AND7 is dually mapped to both Zones 6 and Zone 7. This means that if Zone 7 is disabled (via the
MP/MC mode) then any external memory is still accessible via Zone 6 address space.
D. XCLKOUT is also pinned out on the F2810.
Figure 3. External Interface Block Diagram
P
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