- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382649 > TMX320F2810GHHS (Texas Instruments, Inc.) DIGITAL SIGNAL PROCESSORS PDF資料下載
參數(shù)資料
| 型號(hào)： | TMX320F2810GHHS |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 52/103頁(yè) |
| 文件大?。?/td> | 1341K |
| 代理商： | TMX320F2810GHHS |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)當(dāng)前第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
52
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
watchdog block (continued)
Table 37. WDCNTR Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
7:0
WDCNTR
R/W
0:0
These bits contain the current value of the WD counter. The 8-bit
counter continually increments at the WDCLK rate. If the counter
overflows, then the watchdog initiates a reset. If the WDKEY register
is written with a valid combination, then the counter is reset to zero.
15:8
reserved
R=0
0:0
Table 38. WDKEY Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
7:0
WDKEY
W/R=0
0:0
Writing 0x55 followed by 0xAA will cause the WDCNTR bits to be
cleared. Writing any other value will cause an immediate watchdog
reset to be generated.
15:8
reserved
R=0
0:0
Table 39. WDCR Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
2:0
WDPS(2:0)
R/W
0:0
These bits configure the watchdog counter clock (WDCLK) rate relative
to OSCCLK/512:
000
WDCLK = OSCCLK/512/1
001
WDCLK = OSCCLK/512/1
010
WDCLK = OSCCLK/512/2
011
WDCLK = OSCCLK/512/4
100
WDCLK = OSCCLK/512/8
101
WDCLK = OSCCLK/512/16
110
WDCLK = OSCCLK/512/32
111
WDCLK = OSCCLK/512/64
5:3
WDCHK(2:0)
W/R=0
0:0
The user must ALWAYS write
“
1,0,1
”
to these bits whenever a write to
this register is performed. Writing any other value will cause an
immediate reset to the core (if WD enabled).
6
WDDIS
R/W
0
Writing a 1 to this bit will disable the watchdog module. Writing a 0 will
enable the module. This bit can only be modified if the WDOVERRIDE
bit in the SCSR2 register is set to 1. On reset, the watchdog module is
enabled.
7
WDFLAG
R/W=1
Watchdog reset status flag bit. This bit, if set, indicates a watchdog
reset (WDRST) generated the reset condition. If 0, then it was an
external device or power-up reset condition. This bit remains latched
until the user writes a 1 to clear the condition. Writes of 0 will be ignored.
15:8
reserved
R=0
0:0
P
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMP320F2810GHHS | DIGITAL SIGNAL PROCESSORS |
| TMX320F2810PGFA | DIGITAL SIGNAL PROCESSORS |
| TMP320F2810PGFA | DIGITAL SIGNAL PROCESSORS |
| TMX320F2810PGFAEP | Digital Signal Processors |
| TMP320F2810PGFAEP | Digital Signal Processors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMX320F2810PBKA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSORS |
| TMX320F2810PBKAEP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Digital Signal Processors |
| TMX320F2810PBKS | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSORS |
| TMX320F2810PGFA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSORS |
| TMX320F2810PGFAEP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Digital Signal Processors |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。