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參數(shù)資料
| 型號： | TMX320F2810GHHS |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 68/103頁 |
| 文件大?。?/td> | 1341K |
| 代理商： | TMX320F2810GHHS |
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
68
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
enhanced analog-to-digital converter (ADC) module (continued)
The ADC module in the F2810 and F2812 has been enhanced to provide flexible interface to event managers
A and B. The ADC interface is built around a fast, 12-bit ADC module with a total minimum conversion time of
200 ns (S/H + conversion) per conversion. The ADC module has 16 channels, configurable as two independent
8-channel modules to service event managers A and B. The two independent 8-channel modules can be
cascaded to form a 16-channel module. Although there are multiple input channels and two sequencers, there
is only one converter in the ADC module. Figure 15 shows the block diagram of the F2810 and F2812 ADC
module.
The two 8-channel modules have the capability to autosequence a series of conversions, each module has the
choice of selecting any one of the respective eight channels available through an analog mux. In the cascaded
mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the
conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing
allows the system to convert the same channel multiple times, allowing the user to perform oversampling
algorithms. This gives increased resolution over traditional single-sampled conversion results.
Result Registers
EVB
S/W
ADCSOC
EVA
S/W
Sequencer 2
Sequencer 1
SOC
SOC
ADC Control Registers
70B7h
70B0h
70AFh
70A8h
Result Reg 15
Result Reg 8
Result Reg 7
Result Reg 1
Result Reg 0
Module
ADC
12-Bit
Analog
MUX
ADCIN00
ADCIN07
ADCIN08
ADCIN15
Low-Power
Modes Block
System
Control Block
High-Speed
Prescaler
HALT
HSPCLK
ADCENCLK
C28x
SYSCLKOUT
S/H
S/H
Figure 15. Block Diagram of the F2810 and F2812 ADC Module
P
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