參數(shù)資料
型號(hào)： TPS2459RHB
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC32
封裝： PLASTIC, QFN-32
文件頁(yè)數(shù)： 11/48頁(yè)
文件大?。?/td> 852K
代理商： TPS2459RHB
www.ti.com
SLUS917D – FEBRUARY 2009 – REVISED MAY 2010
Table 5. Register 5: 3.3-V Channel Configuration (Read/Write)
BIT
NAME
DEFAULT
DESCRIPTION
0
3FT0
1
Setting bit increases 3-V fault time by 0.5 ms.
1
3FT1
0
Setting bit increases 3-V fault time by 1 ms.
2
3FT2
0
Setting bit increases 3-V fault time by 2 ms.
3
3FT3
0
Setting bit increases 3-V fault time by 4 ms.
4
3FT4
0
Setting bit increases 3-V fault time by 8 ms.
5
3EN
0
Clearing bit disables 3-V.
6
3UV
0
Setting bit prevents enabling unless OUT3 < bleed-down threshold.
7
3DS
0
Clearing bit disconnects OUT3 bleed-down resistor.
3FT[4:0]
These five bits adjust the 3-V channel fault time. The least-significant bit has a nominal weight of 0.5 ms, so fault times
ranging from 0.5 ms (for code 00001B) to 15.5 ms (for code 11111B) can be programmed. In general the shortest fault time
that fully charges downstream bulk capacitors without generating a fault should be used. See the Setting Fault Time section.
3EN
This bit serves as a master enable for the 3-V channel. Setting this bit allows the 3-V channel to operate normally, provided
the EN3 pin is also asserted. Clearing this bit disables the channel by removing gate drive to the internal pass FET,
regardless of the state of the EN3 pin.
3UV
Setting this bit prevents the 3-V channel from turning on until VOUT3 falls below the bleed-down threshold of 100 mV. This
feature ensures that downstream devices reset by requiring their supply voltage to fall to nearly zero before the channel can
enable them.
3DS
Clearing this bit disconnects the bleed-down resistor that otherwise connects from OUT3 to ground. Systems using redundant
power supplies should clear 3DS to prevent the bleed-down resistor from continuously sinking current.
.
Copyright 2009–2010, Texas Instruments Incorporated
19
Product Folder Link(s): TPS2459
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