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SLUS917D – FEBRUARY 2009 – REVISED MAY 2010
REVISION HISTORY
Changes from Revision A (August 2009) to Revision B
Page
Added New Typical Application Diagram ..............................................................................................................................
1Added EN12 ..........................................................................................................................................................................
2Deleted EN12 ........................................................................................................................................................................
2Deleted m ..............................................................................................................................................................................
3Added ................................................................................................................................................................................
3Deleted m ..............................................................................................................................................................................
3Added ................................................................................................................................................................................
3Added New Block Diagram ...................................................................................................................................................
6Changed 3.3-V Channel Circuitry Block Diagram ................................................................................................................
7Deleted Setting bit makes EN3 and EN12 pins active low. ................................................................................................
16Added This bit must be 0. ...................................................................................................................................................
16Added This bit must be 0. ...................................................................................................................................................
16Deleted Setting bit makes EN3 and EN12 pins active low.Setting bit makes external ENx pins active low; clearing bit
makes pins active high. (Actually, setting this bit reverses polarity of ENPOL R14[5] which will nominally be set as
active low). ..........................................................................................................................................................................
20Added This bit must be 0. ...................................................................................................................................................
20Deleted Setting this bit makes the EN12 and EN3 pins active low. ...................................................................................
20Added This bit must be 0. ...................................................................................................................................................
20Deleted Latches high when OUT12 goes from above VTH_PG to below VTH_PG. .........................................................
21Added This bit is set each time channel is turned on. A second read cycle will indicate true status. ................................
21Deleted Latches high when OUT3 goes from above VTH_PG to below VTH_PG. ...........................................................
21Added This bit is set each time channel is turned on. A second read cycle will indicate true status. ................................
21Added This bit remains set until Register 8 is read. This bit is set each time channel is turned on. A second read
cycle after turn on is required to determine true status. .....................................................................................................
21Added This bit remains set until Register 8 is read. This bit is set each time channel is turned on. A second read
cycle after turn on is required to determine true status. .....................................................................................................
21Added This bit remains set until Register 8 is read. This bit is set each time channel is turned on. A second read
cycle after turn on is required to determine true status. .....................................................................................................
21Added New 12-V Channel Threshold Circuitry Diagram ....................................................................................................
26Added New RC Slew Rate Control Diagram ......................................................................................................................
27Added New 12-V Path Diagram, replaced ORing Thresholds Diagram .............................................................................
30Deleted ORing Thresholds .................................................................................................................................................
30Added 12-V Path ................................................................................................................................................................
30Added ORing Thresholds High Power vs. Low Power .......................................................................................................
31Changed 32 ms ..................................................................................................................................................................
34Added 15.5 ms ....................................................................................................................................................................
34Added the following power; .................................................................................................................................................
34Added New TPS3459 Redundant System Schematic Diagram .........................................................................................
37Copyright 2009–2010, Texas Instruments Incorporated
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