參數(shù)資料
型號(hào)： TPS2459RHB
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC32
封裝： PLASTIC, QFN-32
文件頁(yè)數(shù)： 13/48頁(yè)
文件大?。?/td> 852K
代理商： TPS2459RHB
SLUS917D – FEBRUARY 2009 – REVISED MAY 2010
www.ti.com
Table 6. Register 6: System Configuration (Read/Write)
BIT
NAME
DEFAULT
DESCRIPTION
0
PPTEST
0
12V pulldown test pin. Asserting this pulls the PASS and BLK pins to 0 V.
Clearing bit forces channels to latch off after over-current fault. Setting bit allows channels
1
FLTMODE
0
to automatically attempt restart after fault.
2
ENPOL ENP
0
This bit must be 0.
Setting bit enables 3.3-V channel to prevent reverse current flow.Clearing bit disables 3A
3
3ORON
0
and 3B ORing.
Non-redundant system inrush control bit. Setting bit allows increased inrush current in 12-V
4
12VNRS
0
channel
5
DISA
0
This bit must be set to 1.
6
spare
0
Setting bit allows the 12-V channel to operate despite loss of 3.3 V. For mTCA and AMC
7
DCC
0
applications this bit should be low.
PPTEST
This bit is used for testing the fast turnoff feature of the PASS and BLK pins. Setting this bit enables the fast turnoff drivers for
all four pins. Clearing this bit restores normal operation. PPTEST allows the fast turnoff drivers to operate at full current
indefinitely, whereas they would normally operate for only approximately 15 ms. While using PPTEST the energy dissipated in
the fast turnoff drivers must be externally limited to 1 mJ per driver to prevent damage to the TPS2459.
FLTMODE
Setting this bit allows a channel to attempt an automatic restart after an overcurrent condition has caused it to time out and
shut off. The retry period equals approximately 100 times the programmed fault time. The FLTMODE bit affects all four
channels. If cross-connection is enabled (DCC = 0), a fault on the 3.3-V channel turns off the 12-V channel. If the 3.3-V
channel automatically restarts because FLTMODE = 1, the 12-V channel remains disabled until its enable bit (12EN) is cycled
off and on.
ENPOL
This bit must be 0.
3ORON
Setting this bit allows the 3.3-V ORing function to operate normally. Clearing this bit prevents a VOUT3 > VIN3 condition from
turning off the 3 V channel and forces 3A / 3B ORing to behave as if IN3A >> OUT3A, and IN3B >> OUT3B... This bit is
typically cleared for non-redundant systems.
12VNRS
Setting this bit increases the current limit for the 12-V channel to its maximum value during the initial inrush period that
immediately follows the enabling of the channel. During inrush, the current limit behaves as if 12CL[3:0] = 1111B. After the
current drops below this limit, signifying the end of the inrush period, the current limit returns to normal operation. This
function is intended for use in non-redundant systems with capacitive loads. Setting this bit forces the 12-V current limiters to
behave as though the current limit adjust bits R0[3:0], R3[3:0] are set to 1111 right after EN asserts and will persist until the
channel comes out of current limit or the fault timer times out, whichever comes first.
DISA
This bit must be set to 1.
DCC
Setting this bit disables cross-connection. If DCC = 0, when the 3.3-V channel experiences a fault, both it and the 12-V
channel turn off. If DCC = 1, then the 12-V channel continues to operate even if the 3.3-V channel experiences a fault.
X
20
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS2459
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