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參數(shù)資料
| 型號： | TS68230FN |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HMOS PARALLEL INTERFACE/TIMER |
| 中文描述： | HMO的并行接口/定時器 |
| 文件頁數(shù)： | 13/61頁 |
| 文件大?。?/td> | 2911K |
| 代理商： | TS68230FN |
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PORT GENERAL INFORMATION AND
CONVENTIONS
This section introduces concepts that are generally
applicable to the PI/T ports independent of the cho-
sen mode and submode. For this reason, no parti-
cular port or handshake pins are mentioned ; the
notation H1(H3) indicates that, depending on the
chosen mode and submode, the statement given
may be true for either the H1 or H3 handshake pin.
2.1. UNIDIRECTIONAL VS BIDIRECTIONAL
Figure 1.2 shows the configuration of ports A and B
and each of the handshake pins in each port mode
and submode. In modes 0 and 1, a data direction re-
gister is associated with each of the ports. These re-
gisters contain one bit for each port pin to determine
whether that pin is an input or an output. Modes 0
and 1 are, thus, called unidirectional modes be-
cause each pin assumes a constant direction, chan-
geable only by a reset condition or a programming
change. These modes allow double-buffered data
transfers in one direction. This direction, determined
by the mode and submode definition, is known as
the primary direction. Data transfers in the primary
direction are controlled by the handshake pins. Data
transfers not in the primary direction are generally
unrelated, and single or unbuffered data paths exist.
In modes 2 and 3 there is no concept of primary di-
rection as in modes 0 and 1. Except for port A in
mode 2 (bit I/O), the data direction registers have no
effect. These modes are bidirectional, in that the di-
rection of each transfer (always 8 or 16 bits, double
buffered) is determined dynamically by the state of
the handshake pins. Thus, for example, data may be
transferred out of the ports, followed very shortly by
a transfer into the same port pins. Transfers to and
from the ports are independent and may occur in
any sequence. Since the instantaneous direction is
always determined by the external system, a small
amount of arbitration logic may be required.
2.1.1. CONTROL OF DOUBLE-BUFFERED DATA
PORTS. Generally speaking, the PI/T is a double-
buffered device. In the primary direction, double buf-
fering allows orderly transfers by using the hands-
hake pins in any of several programmable protocols.
(When bit I/O is used, double buffering is not avai-
lable and the handshake pins are used as outputs
or status/interrupt inputs).
Use of double buffering is most beneficial in situa-
tions where a peripheral device and the computer
system are capable of transferring data at roughly
the same speed. Double buffering allows the fetch
operation of the data transmitter to be overlapped
with the store operation of the data receiver. Thus,
throughput measured in bytes or words-per-second
may be greatly enhanced. If there is a large mis-
match in transfer capability between the computer
and the peripheral, little or no benefit is obtained. In
these cases there is no penalty in using double buf-
fering.
2.1.2. DOUBLE-BUFFERED INPUT TRANSFERS.
In all modes, the PI/T supports double-buffered input
transfers. Data that meets the port setup and hold
times is latched on the asserted edge of H1(H3).
H1(H3) is edge sensitive, and may assume any duty
cycle as long as both high and low minimum times are
observed. The PI/T contains a port status register
whose H1S(H3S) status bit is set anytime any input
data that has not been read by the bus master is pre-
sent in the double-buffered latches. The action of
H2(H4) is programmable ; it may indicate whether
there is room for more data in the PI/T latches or it
may serve other purposes. The following options are
available, depending on the mode.
1. H2(H4) may be an edge-sensitive input that is
independent of H1(H3) and the transfer of port
data. On the asserted edge of H2(H4), the
H2S(H4S) status bit is set. It is cleared by the
direct method (refer to
2.3 Direct Method of
Resetting Status
), the RESET pin being as-
serted, or when the H12 enable (H34 enable)
bit of the port general control register is zero.
2. H2(H4) may be a general purpose output pin
that is always negated. The H2S(H4S) status
bit is always zero.
3. H2(H4) may be a general purpose output pin
that is always asserted. The H2S(H4S) status
bit is always zero.
4. H2(H4) may be an output pin in the interlocked
input handshake protocol. It is asserted when
the port input latches are ready to accept new
data. It is negated asynchronously following the
asserted edge of the H1(H3) input. As soon as
the input latches become ready, H2(H4) is a-
gain asserted. When both double-buffered
latches are full, H2(H4) remains negated until
data is removed by a read of port A (port B) data
register. Thus, anytime the H2(H4) output is as-
serted, new input data may be entered by as-
serting H1(H3). At other times transitions of
H1(H3) are ignored. The H2S(H4S) status bit is
always zero. When H12 enable (H34 enable) is
zero, H2(H4) is held negated.
SECTION 2
TS68230
13/61
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