參數(shù)資料
型號： TS68230FN
廠商： 意法半導體
英文描述： HMOS PARALLEL INTERFACE/TIMER
中文描述： HMO的并行接口/定時器
文件頁數(shù)： 38/61頁
文件大?。?/td> 2911K
代理商： TS68230FN
function ; DMA is not used.
PSRR
1 0
The PC4/DMAREQ pin carries the DMAREQ function and is associatedwith double-buffered
transfers controlled by H1. H1 is removed from PI/T’s interrupt structure, and thus, does not cause
interrupt requests to be generated. To obtain DMAREQ pulses, port A control register bit 1 (H1
SVCRQ enable) must be a one.
1 1
The PC4/DMAREQ pin carries the DMAREQ function and is associated with double-buffered
transfers controlled by H3. H3 is removed from the PI/T’s interrupt structure, and thus, does not
cause interrupts requests to be generated. To obtain DMAREQ pulses, port B control register bit
1 (H3 SVCRQ enable) must be one.
SVCRQ Select
PSRR
4 3
0 0
Interrupt Pin Function Select
The PC5/PIRQ pin carries the PC5 function, no interrupt support.
The PC6/PIACK pin carries the PC6 function, no interrupt support.
The PC5/PIRQ pin carries the PIRQ function, supports autovectored interrupts.
The PC6/PIACK pin carries the PC6 function, supports autovectored interrupts.
The PC5/PIRQ pin carries the PC5 function.
The PC6/PIACK pin carries the PIACK function.
The PC5/PIRQ pin carries the PIRQ function, supports vectored interrupts.
The PC6/PIACK pin carries the PIACK function, supports vectored interrupts.
0 1
1 0
1 1
Table 4.2 :
PSRR Port Interrupt Priority Control.
210
000
001
010
011
Highest .......................................Lowest
H1S
H2S
H2S
H1S
H1S
H2S
H2S
H1S
H3S
H3S
H4S
H4S
H4S
H4S
H3S
H3S
210
100
101
110
111
Highest .......................................Lowest
H3S
H4S
H3S
H4S
H4S
H3S
H4S
H3S
H1S
H2S
H1S
H2S
H2S
H1S
H2S
H1S
TS68230
38/61
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