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參數資料
| 型號： | TS68230FN |
| 廠商： | 意法半導體 |
| 英文描述： | HMOS PARALLEL INTERFACE/TIMER |
| 中文描述： | HMO的并行接口/定時器 |
| 文件頁數： | 30/61頁 |
| 文件大?。?/td> | 2911K |
| 代理商： | TS68230FN |
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PBCR
5 4 3
0 X X
1 0 0
1 0 1
1 1 0
1 1 1
H4 Control
Input pin - edge-sensitive status input, H4S is set on an asserted edge.
Output pin - negated, H4S is always cleared.
Output pin - asserted, H4S is always cleared.
Output pin - interlocked input handshake protocol.
Output pin - pulsed input handshake protocol.
PBCR
2
0
1
H4 Interrupt Enable
The H4 interrupt is disabled.
The H4 interrupt is enabled.
PBCR
1
0
1
H3 SVCRQ Enable
The H3 interrupt and DMA request are disabled.
The H3 interrupt and DMA request are enabled.
PBCR
0
0
new data. It is clear when both latches are full and cannot accept new data.
1
The H3S status bit is set when both the initial and final output latches of ports A and B are empty.
The H3S status bit is clear when at least one set of output latches is full.
H3 Status Control
The H3S status bit is set when either the initial or final output latch of ports A and B can accept
3.5. MODE 2 - BIDIRECTIONAL 8-BIT MODE
In mode 2, port A is used for bit I/O with no associa-
ted handshake pins. Port B is used for bidirectional
8-bit double-buffered transfers. H1 and H2, enabled
by the H12 enable bit in the port general control re-
gister, control output transfers, while H3 and H4,
enabled by the port general control register bit H34
enable, control input transfers. The instantaneous
direction of the data is determined by the H1 hand-
shake pin. The port B data direction register is not
used. The port A and port B submode fields do not
affect PI/T operation in mode 2.
3.5.1. PORT A BIT I/O (PIN-DEFINABLE SINGLE-
BUFFERED OUTPUT OR NON-LATCHED IN-
PUT). Mode 2, port A performs simple bit I/O with no
associated handshake pins. This configuration is in-
tended for applications in which several inde-
pendent devices must be controlled or monitored.
Data written to the port A data register is single buf-
fered. If the port A data direction register bit for that
pin is set (output), the output buffer is enabled. If it
is zero (input), data written is still latched but not
available at the pin. Data read from the data register
is either the instantaneous value of the pin (if data
is stable from CS asserted to DTACK asserted, data
on these pins will be guaranteed valid in the data re-
gister) or what was written to the data register, de-
pending on the contents of the port A data direction
register. This is summarized in table 3.3.
Programmable Options Mode 1 - Port A Submode XX and Port B Submode X1
(continued)
TS68230
30/61
相關PDF資料 |
PDF描述 |
|---|---|
| TS68230 | HMOS PARALLEL INTERFACE/TIMER |
| TS68230CP10 | HMOS PARALLEL INTERFACE/TIMER |
| TS68230CP8 | HMOS PARALLEL INTERFACE/TIMER |
| TS68230P | HMOS PARALLEL INTERFACE/TIMER |
| TS68230CFN8 | HMOS PARALLEL INTERFACE/TIMER |
相關代理商/技術參數 |
參數描述 |
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| TS68230MC1B/C10 | 制造商:e2v technologies 功能描述: |
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| TS68230P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HMOS PARALLEL INTERFACE/TIMER |
| TS68302 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Integrated Multiprotocol Processor IMP |
| TS68302CA1B/C16 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Integrated Multiprotocol Processor IMP |
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