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參數(shù)資料
| 型號： | TS68230FN |
| 廠商： | 意法半導體 |
| 英文描述： | HMOS PARALLEL INTERFACE/TIMER |
| 中文描述： | HMO的并行接口/定時器 |
| 文件頁數(shù)： | 27/61頁 |
| 文件大小： | 2911K |
| 代理商： | TS68230FN |
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5. H4 may be an output pin in the pulsed input
handshake protocol. It is asserted exactly as in
the interlocked input protocol above, but never
remains asserted longer than four clock cycles.
Typically, a four clock cycle pulse is generated.
But in the case that a subsequent H3 asserted
edge occurs before termination of the pulse, H4
is negated asynchronously. Thus, anytime after
the leading edge of the H4 pulse, new data may
be entered in the double-buffered input latches.
The H4S status bit is always clear. When H34
enable is clear, H4 is held negated.
For pins used as outputs, the data path consists of
a single latch driving the output buffer. Data written
to the port’s data register does not affect the opera-
tion of any handshake pin, status bit, or any other as-
pect of the PI/T. Thus, output pins may be used
independently of the input transfer.
The programmable options of the H2 pin are :
1. H2 may be an edge-sensitive input pin inde-
pendent of H1 and the transfer of port data. On
the asserted edge of H2, the H2S status bit is
set. It is cleared by either the RESET pin being
asserted, writing a one to the particular status
bit in the port status register (PSR), or when the
H12 enable bit of the port general control re-
gister is clear.
2. H2 may be a general-purpose output pin that
is always negated. The H2S status bit is al-
ways clear.
3. H2 may be a general-purpose output pin that
is always asserted. The H2S status bit is al-
ways clear.
Programmable Options Mode 1 - Port A Submode XX and Port B Submode X0
PACR
7 6
0 0
Port A Submode
Submode XX
PACR
5 4 3
0 X X
1 X 0
1 X 1
H2 Control
Input pin - edge-sensitive status input, H2S is set on an asserted edge.
Output pin - negated, H2S is always cleared.
Output pin - asserted, H2S is always cleared.
PACR
2
0
1
H2 Interrupt Enable
The H2 interrupt is disabled.
The H2 interrupt is enabled.
PACR
1
0
1
H1 SVCRQ Enable
The H1 interrupt is disabled.
The H1 interrupt is enabled.
PACR
0
X
H1 Status Control.
H1 is an edge-sensitive status input. H1S is set by an asserted edge of H1.
PBCR
7 6
0 0
Port B Submode
Submode X0.
TS68230
27/61
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