參數(shù)資料
型號： TS68332DESC02ZC
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： High performance 32-bit integrated microcontroller
中文描述： 32-BIT, 20.97 MHz, MICROCONTROLLER, CPGA132
封裝： CERAMIC, PGA-132
文件頁數(shù)： 16/56頁
文件大小： 1510K
代理商： TS68332DESC02ZC
16
TS68332
2118A–HIREL–03/02
Notes:
1. AllACtimingisshownwithrespectto20%V
DD
and70%V
DD
levelsunlessotherwisenoted.
2. Minimumsystemclockfrequencyisfourtimesthecrystalfrequency,subjecttospecifiedlimits.
3. Whenanexternalclockisused,minimumhighandlowtimesarebasedona50%dutycycle.Theminimumallowablet
Xcyc
periodisreducedwhenthedutycycleoftheexternalclocksignalvaries.Therelationshipbetweenexternalclockinputduty
cycleandminimumt
Xcyc
isexpressed:
Minimumt
Xcyc
period=minimumt
XCHL
/(50%-externalinputdutycycletolerance)
4. ParametersforanexternalclocksignalappliedwhiletheinternalPLLisdisabled(MODCLKpinheldlowduringreset).Does
notpertaintoanexternalVCOreferenceappliedwhilethePLLisenabled(MODCLKpinheldhighduringreset).Whenthe
PLLisenabled,theclocksynthesizerdetectssuccessivetransitionsofthereferencesignal.Iftransitionsoccurwithinthe
correctclockperiod,rise/falltimesanddutycycleareatcritical.
5. Specification9Aistheworst-caseskewbetweenASandDSorCS.Theamountofskewdependsontherelativeloadingof
thesesignals.Whenloadsarekeptwithinspecifiedlimits,skewwillnotcauseASandDStofalloutsidethelimitsshownin
specification9.
6. Ifmultiplechipselectsareused,CSwidthnegated(specification15)appliestothetimefromthenegationofaheavily
loadedchipselecttotheassertionofalightlyloadedchipselect.TheCSwidthnegatedspecificationbetweenmultiplechip
selectsdoesnotapplytochipselectsbeingusedforsynchronousECLKcycles.
7. HoldtimesarespecifiedwithrespecttoDSorCSonasynchronousreadsandwithrespecttoCLKOUTonfastcyclereads.
Theuserisfreetouseeitherholdtime.
8. Maximumvalueisequalto(t
cyc
/2)+25ns.
9. Iftheasynchronoussetuptime(specification47A)requirementsaresatisfied,theDSACK[1:0]lowtodatasetuptime(spec-
ification31)andDSACK[1:0]lowtoBERRlowsetuptime(specification48)canbeignored.Thedatamustonlysatisfythe
data-intoclocklowsetuptime(specification27)forthefollowingclockcycle.BERRmustsatisfyonlythelateBERRlowto
clocklowsetuptime(specification27A)forthefollowingclockcycle.
10. Toensurecoherencyduringeveryoperandtransfer,BGwillnotbeassertedinresponsetoBRuntilafterallcyclesofthe
currentoperandtransferarecompleteandRMCisnegated.
11. IntheabsenceofDSACK[1:0],BERRisanasynchronousinputusingtheasynchronoussetuptime(specification47A).
12. AfterexternalRESETnegationisdetected,ashorttransitionperiod(approximately2t
cyc
)elapses,thentheSIMdrives
RESETlowfor512t
cyc.
13. ExternalassertionoftheRESETinputcanoverlapinternally-generatedresets.Toinsurethatanexternalresetisrecog-
nizedinallcases,RESETmustbeassertedforatleast590CLKOUTcycles.
14. ExternallogicmustpullRESEThighduringthisperiodinorderfornormalMCUoperationtobegin.
15. Addressaccesstime=(2.5+WS)t
cyc
-t
CHAV
-t
DICL.
Chipselectaccesstime=(2+WS)t
cyc
-t
CLSA
-t
DICL
.
Where:WS=numberofwaitstates.Whenfastterminationisused(2clockbus)WS=-1.
76
t
MSH
Modeselectholdtime
0
-
0
-
ns
77
t
RSTA
RESETassertiontime
(12)
4
-
4
-
t
CYC
78
t
RSTR
RESETrisetime
(13)(14)
-
10
-
10
t
CYC
Table6.
ACTiming.V
DD
andV
DDSYN
=5.0V
DC
±10%for16.78MHzand5.0V
DC
±5%for20.97MHz;V
SS
=0V
DC
;
T
C
=-55°Cto+125°Cor-40°Cto+85°C(Continued)
(1)
Number
Symbol
Parameter
16.78MHz
20.97MHz
Unit
Min
Max
Min
Max
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