參數(shù)資料
型號(hào): TS68332DESC02ZC
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: High performance 32-bit integrated microcontroller
中文描述: 32-BIT, 20.97 MHz, MICROCONTROLLER, CPGA132
封裝: CERAMIC, PGA-132
文件頁數(shù): 46/56頁
文件大?。?/td> 1510K
代理商: TS68332DESC02ZC
46
TS68332
2118A–HIREL–03/02
13-bitsProgrammableBaudRateModulusCounter
Even/oddParityGenerationAndDetection
QSM-enhancedSCIReceiverFeatures
TwoIdle-lineDetectModes
ReceiverActiveFlag
13-bitProgrammableBaudRateModulusCounter:
Abaudratemoduluscounterhas
beenaddedtoprovidetheuserwithmoreflexibilityinchoosingthecrystalfrequencyfor
thesystemclock.ThemoduluscounterallowstheSCIbaudrategeneratortoproduce
standardtransmissionfrequenciesforawiderangeofsystemclocks.Theuserisno
longerconstrainedtoselectcrystalfrequenciesbasedonthedesiredserialbaudrate.
Thiscounterbaudratesfrom64baudto524baudwitha16.78MHzsystemclock.
Even/oddParityGenerationandDetection:
Theusernowhasthechoiceeitherofseven
oreightdatabitsplusoneparitybit,orofeightorninedatabitswithnoparitybit.Even
oroddparityisavailable.Thetransmitterautomaticallygeneratestheparitybitfora
transmittedbyte.Thereceiverdetectswhenaparityerrorhasoccurredonareceived
byteandsetsaparityerrorflag.
TwoIdle-lineDetectModes:
StandardAtmel-GrenobleSCIsystemsdetectanidleline
when10or11consecutivebit-timesareallones.Usedwiththereceiverwakeupmode,
thereceivercanbeawakenedprematurelyifthemessageprecedingthestartoftheidle
linecontainedonesinadvanceofitsstopbit.Thenew(second)idle-linedetectmode
onlystartscountingidletimeafteravalidstopbitisreceived,whichensurescorrectidle-
linedetection.
ReceiverActiveFlag(RAF):
ReceiverActiveFlag(RAF)indicatesthestatusofthe
receiver.Itissetwhenapossiblestartbitisdetectedandisclearedwhenanidlelineis
detected.RAFisalsoclearedifthestartbitisdeterminedtobelinenoise.Thisflagcan
beusedtopreventcollisionsinsystemswithmultiplemasters.
ForfurtherinformationrefertotheSystemIntegrationModuleManual.
StandbyRAM(withTPU
emulation)
TheTS68332contains2-KbytesofstandbyRAM.Thissectiondescribestheoperation
andcontroloftheRAMmodule.
Overview
TheRammodulecontains2048bytesoffullystaticRAM,poweredbyV
DD
innormal
operation.TheentirearraymaybeusedasstandbyRAMifpowerissuppliedtothe
V
STBY
pin.SwitchingbetweenV
DD
andV
STBY
occursautomatically.
TheRAMmaybeusedasgeneral-purposememoryfortheMCU,providingfast,two-
clockaccessestotheCPU.Typically,theRAMisusedforprogramcontrolstacksand
frequentlymodifieddatavariables.TheCPUmayreadorwritebyte,word,orlong-word
data.
TheRAMmayalsobeusedasmicrocodecontrolmemoryfortheTimeProcessorUnit
(TPU).TheTPUmustbeplacedinemulationmodetousetheRAMinthismanner
whichallowsuserstodeveloptheirownmicrocodeprimitives.
RAMArrayAddressing
TheRAMarraycanbeplacedanywhereintheaddressmapofthearraybaseaddress
(RAMBAR),providedthatitisona2-Kbytesboundaryanddoesnotoverlapthethree
RAMmodulecontrolregistersusedforcontrolandtesting.RAMBARcanbewrittenonly
onceafterreset.ThispreventstheRAMarraybeingaccidentallyremappedbysoftware.
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