參數(shù)資料
型號： TS68332MR16
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： High performance 32-bit integrated microcontroller
中文描述： 32-BIT, 16.78 MHz, MICROCONTROLLER, CPGA132
封裝： CERAMIC, PGA-132
文件頁數(shù)： 35/56頁
文件大?。?/td> 1510K
代理商： TS68332MR16
35
TS68332
2118A–HIREL–03/02
BusControlSignals
TheMCUinitiatesabuscyclebydrivingtheaddress,size,function,code,and
read/writeoutputs.Atthebeginningofabuscycle,thesizesignals(SIZ1,SIZ0)are
drivenalongwiththefunctioncodesignals.SIZ1andSIZ0indicatethenumberofbytes
remainingtobetransferredduringanoperandcycle(consistingofoneormorebus
cycles).Table8showstheencodingofSIZ1andSIZ0.Theread/write(R/W)signal
determinesthedirectionofthetransferduringabuscycle.Theread-modify-writecycle
signal(RMC)isassertedatthebeginningofthefirstbuscycleofaread-modify-write
operation,andremainsasserteduntilcompletionofthefinalbuscycleoftheoperation.
BusCycleTermination
Signals
Duringbuscycles,externaldevicesassertthedatatransferandsizeacknowledgesig-
nalsDSACK1and/orDSACK0aspartofthebusprotocol.Duringareadcycle,this
signalstheMCUtoterminatethebuscycleandtolatchthedata.Duringawritecycle,
thisindicatesthattheexternaldevicehassuccessfullystoredthedataandthatthecycle
mayterminate.ThesesignalsalsoindicatetotheMCUthesizeoftheportforthebus
cyclejustcompleted.
Thebuserror(BERR)signalisalsoabuscycleterminationindicatorandcanbeusedin
theabsenceofDSACKxtoindicateabuserrorcondition.Itcanalsobeassertedincon-
junctionwithDSACKxtoindicateabuserrorcondition,provideditmeetsthe
appropriatetiming.Additionally,theBERRandHALTsignalscanbeassertedsimulta-
neously,inlieuof,orinconjunctionwith,theDSACKxsignals.
TheinternalbusmonitorcanbeusedtogeneratetheBERRsignalforinternalandinter-
nal-to-externaltransfers.AnexternalbusmastermustprovideitsownBERRgeneration
anddrivetheBERRpin,sincetheinternalBERRmonitorhasnoinformationabout
transfersinitiatedbyanexternalbusmaster.
Finally,theautovector(AVEC)signalcanbeusedtoterminateinterruptacknowledge
cycles,indicatingthattheMCUshouldinternallygenerateavectornumbertolocatean
interrupthandlerroutine.AVECisignoredduringallotherbuscycles.
DynamicBusSizing
TheMCUdynamicallyinterruptstheportsizeoftheaddresseddeviceduringeachbus
signal,allowingoperandtransferstoorfrom8-and16-bitports.Duringanoperand
transfercycle,theslavedevicesignalsitsportsize(byteorword)andindicatescomple-
tionofthebuscycletotheMCUthroughtheuseoftheDSACKxencodingsand
assertionresults.RefertoTable9forDSACKxencodingsandassertionresults.For
example,iftheMCUisexecutinganinstructionthatreadsalong-wordoperandfroma
16-bitport,theMCUlatchesthe16bitsofvaliddataandrunsanotherbuscycleto
obtaintheother16bits.
Dynamicbussizingrequiresthattheportionofthedatabusforatransfertoorfroma
particularportsizebefixed.Forexamplean8-bitportmustresideondatabusbits15-
8.
TheSIZxsignalsalsoformpartofthebussizingprotocol.Theseoutputsindicatethe
remainingnumberorbytestobetransferredduringthecurrentbuscycle.
Table8.
SizeSignalEncoding
SIZ1
SIZ2
TransferSize
0
1
Byte
1
0
Word
1
1
3Byte
0
0
LongWord
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