參數(shù)資料
型號(hào): TS68332MR16
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: High performance 32-bit integrated microcontroller
中文描述: 32-BIT, 16.78 MHz, MICROCONTROLLER, CPGA132
封裝: CERAMIC, PGA-132
文件頁數(shù): 36/56頁
文件大小: 1510K
代理商: TS68332MR16
36
TS68332
2118A–HIREL–03/02
BusOperation
TheMCUbusisusedinanasynchronousmanner.Theexternaldevicesconnectedto
thebuscanoperateatclockfrequenciesdifferentfromtheclockfortheMCU.Busoper-
ationusesthehandshakelines(AS,DS,DSACK1,DSACK0,BERRandHALT)to
controldatatransfers.DecodingthesizeoutputsandloweraddresslineA0provides
strobesthatselecttheactiveportionofthedatabus.Theslavedevice(memoryor
peripheral)thenrespondsbyplacingtherequesteddataonthecorrectportionofthe
databusforareadcycleorlatchingthedataonawritecycle,andassertingthe
DSACK1/DSACK0combinationthatcorrespondstotheportsizetoendthecycle.Ifno
slaverespondsortheaccessisinvalid,externalcontrollogicassertstheBERR,or
BERRandHALT)signal(s)toabortorretrythebuscycle,respectively.
FastTerminationCycles
Withanexternaldevicethathasafastaccesstime,thechip-selectcircuitfast-termina-
tionoptioncanprovideatwo-cycleexternalbustransfer.Sincethechipselectcircuits
aredrivenfromthesystemclock,thebuscycleterminationisinherentlysynchronized
withthesystemclock.
BusExceptionControlCycles
ThebusarchitecturerequiresassertionofDSACKxfromanexternaldevicetosignal
thatabuscycleiscomplete.DSACKxorAVECisnotassertedinthesecases:
Theexternaldevicedoesnotrespond
Nointerruptvectorisprovided
Variousotherapplication-dependenterrorsoccur
ThisMCUhasabuserrorinput(BERR)whennodevicerespondsbyasserting
DSACKxorwithinanappropriateperiodoftimeaftertheMCUassertstheAVEC.This
allowsthecycletoterminateandtheMCUtoenterexceptionprocessingfortheerror
condition.Anothersignalthatisusedforbusexceptioncontrolisthehaltsignal
(HALT).Thissignalcanbeassertedbyanexternaldevicefordebuggingpurposesto
causesinglebusoperationor(incombinationwithBERR)aretryofabuscycleinerror.
Table9.
DSACKCodesandResults
DSACK1
DSACK0
Result
1
(Negated)
1
(Negated)
Insertwaitstatesincurrentbuscycle
1
(Negated)
0
(Asserted)
Completecycle–Databusportsizeis8-bits
0
(Asserted)
1
(Negated)
Completecycle–Databusportsizeis16-bits
0
(Asserted)
0
(Asserted)
Reserved
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