參數(shù)資料
型號： TSC2302IRGZR
元件分類： Codec
英文描述： PROGRAMMABLE TOUCH SCREEN CONTROLLER WITH STEREO AUDIO CODEC
中文描述： 可編程觸摸屏控制器，立體聲編解碼器
文件頁數(shù)： 65/81頁
文件大小： 1211K
代理商： TSC2302IRGZR
www.ti.com
www.ti.com
TSC2302
SLAS394–JULY 2003
Power Consumption
The TSC2302 provides maximum flexibility to the user for control of power consumption. Towards that end, every
section of the TSC2302 audio codec can be independently powered down. The power down status of the
different sections is controlled by Reg 05h in Pg 2. The analog bypass path, headphone amplifier, mono output,
stereo DAC, left channel ADC, right channel ADC, microphone bias, crystal oscillator, and oscillator clock buffer
sections can all be powered down independently. It is recommended that the end-user power down all unused
sections whenever possible in order to minimize power consumption. Below is a table showing power
consumption in different modes of operation.
Table 24. Power Consumption by Mode of Operation
OPERATING MODE DESCRIPTION
REGISTER 05H BIT VALUES
POWER CONSUMPTION
TYP
UNITS
15
14
13
12
11
10
9
8
6
5
4
STEREO RECORD AND PLAYBACK
Mono record, stereo playback, 48 kHz
0
0
1
1
1
0
0
1
1
0
0
45
mW
Mono record, stereo playback, 8 kHz
0
0
1
1
1
0
0
1
1
0
0
38
mW
Stereo record, stereo playback, 48 kHz
0
0
1
1
1
0
0
0
1
0
0
60
mW
Stereo record, stereo playback, 8 kHz
0
0
1
1
1
0
0
0
1
0
0
48
mW
STEREO PLAYBACK ONLY
Headphone playback only, 48 kHz
0
0
1
0
1
0
1
1
1
0
0
34
mW
RECORD ONLY
Stereo line record only, 48 kHz
0
0
1
1
1
1
0
0
1
0
0
34
mW
Stereo line record only, 8 kHz
0
0
1
1
1
1
0
0
1
0
0
26
mW
Mono record, 48 kHz
0
0
1
1
1
1
0
1
1
0
0
19
mW
Mono record only, 8 kHz
0
0
1
1
1
1
0
1
1
0
0
15
mW
ANALOG BYPASS
Line in to headphone out
0
0
0
0
1
1
1
1
1
0
0
13
mW
POWER DOWN
Power down all
1
1
X
X
X
X
X
X
X
0
0
0.5
μW
Power down, VCM enabled
1
0
X
X
X
X
X
X
X
0
0
0.8
μW
TSC2302 AUDIO CONTROL REGISTERS
TSC2302 Audio Control Register (Page 2, Address 00H)
The audio control register of the TSC2302 controls the digital audio interface, the microphone preamp gain, the
record multiplexer settings, and the ADC highpass filter pole. This register determines which ADC high pass filter
response is selected, as well as which audio inputs are connected to the stereo ADCs. The gain of the MIC input
(0 to 12 dB) is also selected. This register is also used to tell the data converters the frequency of MCLK, along
with the frequency of LRCLK (ADC and DAC sample rates). The format of the audio data is also selected.
The audio control register is formatted as follows:
BIT 15
MSB
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LSB
HPF1
HPF0
INML1
INML0
INMR1
INMR0
MICG1
MICG0
MCLK1
MCLK0
I2SFS3
I2SFS2
I2SFS1
I2SFS0
I2SFM1
I2SFM0
65
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