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參數(shù)資料
| 型號： | TVP3409-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS) |
| 中文描述： | 先進的視頻接口盒（雙鎖相環(huán)，視頻接口調(diào)色器真彩色的CMOS） |
| 文件頁數(shù)： | 17/57頁 |
| 文件大?。?/td> | 312K |
| 代理商： | TVP3409-135 |
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2–5
This register is autoincrementing when reading the LUT. When written, the RMA reads the RAMDAC color
RAM data into the LUT data register then the RMA increments by one. When the three reads from the LUT
data register are complete, the device transfers new RAMDAC color RAM data at the RMA address into the
LUT data register and the RMA increments by one again. When using the RMA for access to the indexed
registers, write a value one less than the desired index. The RMA register increments by one before using
the index to access the information being read or written.
2.2.3
Look-Up Table Data Register (LUT)
This register is the data port through which reads and writes are made to the RAMDAC color RAM. The
write-mode address register or read-mode address register specifies which RAMDAC color RAM location
is to be accessed. This register is an 8-bit port to a 24-bit location. Three accesses are needed to read or
write the LUT data register. Because both the write-mode address and read-mode address registers are
autoincrementing, accesses to this port should be made three at a time to avoid leaving a partially read or
written LUT data register. A partially written data register is not transferred to the RAMDAC color RAM. The
blue value must be written before the RAMDAC color RAM is updated.
2.2.4
Pixel Read Mask Register (RMR)
The contents of the RMR can be accessed by the MPU at any time and are not initialized on power up. The
RMR bits are logically ANDed with the 8-bit pixels in pseudocolor mode. In true-color modes, pixels are not
modified by the RMR. A logic one stored in a data bit of the RMR leaves the corresponding bit in the pixel
unchanged. A logic 0 in the RMR sets the pixel bit to 0. Bit D0 of the RMR corresponds to pixel bit P0.
Reading the RMR four times without accessing another RAMDAC register directs the next (fifth) read or
write access to control register 0. The sixth consecutive read from the RMR returns the MIR. The seventh
consecutive read from the RMR returns the DIR (see Table 2–7).
Table 2–7. Accessing the RMR Enables Indirect Access of CR0, MIR, and DIR
RMR
READ
NO.
REGISTER
NAME
REGISTER
TYPE
7
6
5
4
3
2
1
0
5
CR0
Read
Write
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
6
MIR
Read
Only
1
0
0
0
0
1
0
0
7
DIR
Read
Only
0
0
0
0
1
0
0
1
The eighth, ninth, and tenth consecutive reads from the RMR return don’t care values. These states are
defined in the back-door state machine to maintain compatibility with the ATT20C409, ATT20C499, and
ATT20C498 test registers. These test registers are not being implemented in the TVP3409 and, therefore,
do not return usable information (see Figure 2–1).
2.2.5
Manufacturer’s Identification Register (MIR)
This 8-bit register contains an 8-bit value to identify the manufacturer of the RAMDAC. The MIR is read by
reading the RMR six times without accessing any other RAMDAC register. The first four reads return the
contents of the RMR. The fifth read returns the CR0 contents. The sixth read returns the MIR contents (97
hex). The seventh read returns the DIR contents.
2.2.6
Device Identification Register (DIR)
This 8-bit register contains an 8-bit value to identify the type of RAMDAC. The DIR is read by reading the
RMR seven times without accessing any other RAMDAC register. The TVP3409 returns the value 09 hex.
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PDF描述 |
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| TVP3703-170 | Video Interface PALETTE Exract(雙PLL，先進的視頻接口調(diào)色器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3409-135CFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3409-135FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3409-170CFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3409-170FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3703 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC |
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