參數(shù)資料
型號(hào)： TVP3409-135
廠商： Texas Instruments, Inc.
英文描述： Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
中文描述： 先進(jìn)的視頻接口盒（雙鎖相環(huán)，視頻接口調(diào)色器真彩色的CMOS）
文件頁(yè)數(shù)： 24/57頁(yè)
文件大?。?/td> 312K
代理商： TVP3409-135
2–12
2.5
This section describes how to change the internal synthesizer frequencies without corrupting the on-chip
pixel color RAM.
Changing Clock Frequencies
1.
Power down the chip by setting CR0(3) = 1. The registers retain their values and can be read from
and written to. The RAM cannot be read from or written to during this time.
2.
Program a delay of approximately 300
μ
s. The delay varies depending on the noise in the system
and the signals connected to the RAMDAC.
3.
Change the synthesizer register settings and/or change the frequency select bits/lines.
4.
Program another delay of approximately 300
μ
s. This varies depending on the noise in the
system and the signals connected to the RAMDAC.
5.
Power up the chip by setting CR0(3) = 0. The registers retain their values and can be read from
and written to. The RAM can now be read from or written to.
The data (colors) integrity of the pixel color RAM should be intact. To add further protection to the values
in the color RAM, copy the pixel color RAM to system memory before changing clock frequencies. Copy the
values back after the frequency has settled.
2.6
Functional Descriptions
The following sections contain functional descriptions of the device.
2.6.1
State machine access to the extended registers is provided to give backward compatibility to the
ATT20C498 RAMDAC. Indirect access to the extended registers is described by a state diagram shown in
Figure 2–1. Table 2–16 indicates the register access in each state. The extended registers accessible in this
manner are CR0, MIR, and DIR.
State Machine Access to Extended Registers
To read CR0, read the RMR five times. The fifth read returns the contents of CR0. To write CR0, read the
RMR four times. This sets an internal flag allowing access to control register 0. The next write is directed
to control register 0. The MIR and DIR registers are accessed in a similar manner as shown by
Figure 2–1. The sixth read of the RMR returns the contents of the MIR (read only). The seventh read of the
RMR returns the contents in the DIR (read only). The eighth, ninth, and tenth reads of the RMR return don’t
care values and are required for compatibility with the ATT20C4xx series devices. An additional read resets
the state machine back to state 0.
Table 2–15 indicates I/O operations that reset the state machine to state 0. Any write operation resets the
state machine to state 0.
Table 2–15. I/O Transition and Logic-Level Combinations
that Reset the State Machine to State 0
WR
↓
↓
↓
↓
RS1
RS0
L
L
L
H
H
L
H
H
2.6.2
Indexing provides another way to access the extended registers and it is the only way to access CR1, CC,
and the clock synthesizer register sets (see Table 2–5). CR0 must be accessed through state machine
addressing to set bit 0 to a 1 before indexed accessing can be used. The CR0, MIR, and DIR registers can
be accessed either by the RMR or by indexing.
Indexed Access to Extended Registers
相關(guān)PDF資料
PDF描述
TVP3703-170 Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器)
TVP3703-135 Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器)
TVP3703FN VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC
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參數(shù)描述
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TVP3409-170CFN 制造商:Rochester Electronics LLC 功能描述:- Bulk
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TVP3703 制造商:TI 制造商全稱:Texas Instruments 功能描述:VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC
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