參數(shù)資料
型號(hào)： TVP3409-135
廠(chǎng)商： Texas Instruments, Inc.
英文描述： Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
中文描述： 先進(jìn)的視頻接口盒（雙鎖相環(huán)，視頻接口調(diào)色器真彩色的CMOS）
文件頁(yè)數(shù)： 18/57頁(yè)
文件大?。?/td> 312K
代理商： TVP3409-135
2–6
2.2.7
Control register 0 is written to or read by the MPU. CR0 is not initialized at power on. CR0 bit 0 is the least
significant bit (LSB) in the control register and corresponds to D0 of the MPU port. Table 2–8 defines the
bits of the control register.
Control Register 0 (CR0)
CR0 bits (7–4) determine the color mode as shown in Table 2–17.
Setting CR0(3) to a 1 places the RAMDAC in power-down mode. In the power-down state, the device retains
the information in the color look-up table. Access to the color look-up table is disabled during the
power-down mode. The internal registers can be written to while the device is in the power-down mode. The
crystal oscillator and clock synthesizers are powered down separately.
The CR0(2) bit is reserved.
The 8/6 select bit CR0(1) determines whether the MPU port reads and writes 8 bits or 6 bits of color data
to the color look up table RAM. In 6-bit mode, color data is on the lower 6 bits of the data bus, with D0 being
the LSB and D5 the most significant bit (MSB) of color data. When writing color data, D6 and D7 are ignored.
During color read cycles, D6 and D7 are logic 0. Note that in the 6-bit mode, the full scale output current is
about 1.5% lower than when in the 8-bit mode. This is a result of the two LSBs of each 8-bit DAC always
being a logic 0 in the 6-bit mode. In the 8-bit color mode, bit D0 is the color data LSB and bit D7 is the MSB.
The CR0(0) bit controls access to the extended registers.
This register is operational upon power up. It can be read or written to by the MPU at any time and it is not
initialized. All bits are set to 0 upon asserting RESET. To read from or write to this register, use the internal
state machine for access by reading the RMR (see Table 2–3).
Table 2–8. Control Register 0
BIT
NAME
DESCRIPTION
CR0(7–4)
Color Mode
These bits control the color modes (see Tables 2–17).
CR0(3)
Power Down
(RAMDAC)
Logic 0: Normal operation
Logic 1: Sleep
CR0(3) powers the RAMDAC off. The device does not power up for MPU updates.
The data in the LUT is maintained during power down. Internal registers can be
accessed while the RAMDAC is powered down. CR1(3,2) powers down the clock
synthesizers (for green PC compatibility).
CR0(2)
Reserved
CR0(1)
8/6 Select
Logic 0: 6-bit data to the DAC
Logic 1: 8-bit data to the DAC
A logic 0 specifies 6 bits per DAC operation (256K possible colors). A logic 1
specifies 8 bits per DAC operation (16M possible colors).
CR0(0)
Extended Register
Enable (Indirect or
Indexed Access)
Logic 0: Index accesses disabled to extended registers.
Logic 1: Index accesses enabled to extended registers.
Bit 0 controls access to the extended registers. When bit 0 is a logic 0, access to the
extended registers is enabled by multiple accesses to the RMR (state machine
addressing). This does not allow access to CR1, CC, or the clock configuration
registers. When this bit is a logic 1, all extended registers can be accessed with
indexed addressing using the WMA or RMA register as an address pointer and
RS(1,0)= 10 for the data register.
相關(guān)PDF資料
PDF描述
TVP3703-170 Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器)
TVP3703-135 Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器)
TVP3703FN VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3409-135CFN 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3409-135FN 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3409-170CFN 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3409-170FN 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3703 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC
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