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參數(shù)資料
| 型號： | TVP3409-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS) |
| 中文描述： | 先進(jìn)的視頻接口盒（雙鎖相環(huán)，視頻接口調(diào)色器真彩色的CMOS） |
| 文件頁數(shù)： | 25/57頁 |
| 文件大?。?/td> | 312K |
| 代理商： | TVP3409-135 |
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2–13
To use this method, set CR0(0) = 1 using state machine accessing (multiple accesses to the RMR). Write
the write-mode address register (WMA) with the address of the register to be read or written. Set RS(1,0)
= HL. Perform a read or write operation. The value is read from or written to the desired register. The address
register does not increment automatically. When the RMA is used for indexing, write a value 1 less than the
desired value. The RMA increments before being used as an index. The addresses of the registers
accessible by indexing are listed in the indexed access column in Table 2–4 and Table 2–5.
0
1
2
3
4
CR0
5
MIR
6
DIR
7
8
9
10
I/O OP
I/O OP
I/O OP
I/O OP
I/O OP
I/O OP
I/O OP
I/O OP
I/O OP
I/O OP
Read
of RMR
Read
of RMR
Read
of RMR
Read
of RMR
Read or
Write
of RMR
Read
of RMR
Read
of RMR
Read
of RMR
Read
of RMR
Read
of RMR
NOTE A: I/O OP is any I/O write to 3C6, 3C7, 3C8, or 3C9 (see Table 2–2).
Figure 2–1. State Diagram for Indirect Access to Extended Registers
Table 2–16. Access to CR0, MIR, and DIR Registers
STATE TABLE
STATE
STATE ENTRY CONDITIONS
STATE ACTIVITY
0
Any I/O write
Normal I/O access
1
Read of RMR while in state 0
Normal I/O access
2
Read of RMR while in state 1
Normal I/O access
3
Read of RMR while in state 2
Normal I/O access
4
Read of RMR while in state 3
Normal I/O access
5
Read or write of RMR while in state 4
I/O access to CR0
6
Read of RMR while in state 5
Returns MIR, 97 hex
7
Read of RMR while in state 6
Returns DIR, 09 hex
8
Read of RMR while in state 7
Normal I/O access
9
Read of RMR while in state 8
Normal I/O access
10
Read of RMR while in state 9
Normal I/O access
2.6.3
Color Modes
The TVP3409 provides nine different color modes that are selectable by programming control register 0 bits
CR0(7–4) (see Table 2–17).
In true color modes with multiple or fractional clocks per pixel, a clock multiplier provides the internal load
pulse that latches the data into a 16- or 24-bit pixel. True color modes bypass the look-up table and are not
gamma corrected. The modes are discussed in the following sections.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TVP3703-170 | Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器) |
| TVP3703-135 | Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器) |
| TVP3703FN | VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC |
| TVP5020TQFP | NTSC/PAL VIDEO DECODER |
| TVP5031 | NTSC/PAL VIDEO DECODER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3409-135CFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3409-135FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3409-170CFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3409-170FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3703 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC |
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