參數(shù)資料
型號(hào)： TVP70025IPZP
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： GREEN, PLASTIC, HTQFP-100
文件頁數(shù)： 33/59頁
文件大?。?/td> 519K
代理商： TVP70025IPZP
SLES232B
– JUNE 2008 – REVISED MAY 2011
Input Mux Select 2
Subaddress
1Ah
Default (C2h)
7
6
5
4
3
2
1
0
SOG LPF SEL [1:0]
CLP LPF SEL [1:0]
CLK SEL
VS SEL
PCLK SEL
HS SEL
SOG LPF SEL [1:0]: SOG low-pass filter selection. The SOG low-pass filter can be used to attenuate glitches present on
the SOG input. Excessive filtering can lead to sync detection issues and increased sample clock jitter.
00 = 2.5-MHz low-pass filter
01 = 10-MHz low-pass filter
10 = 33-MHz low-pass filter
11 = Low-pass filter bypass (default)
NOTE: The SOG LPF setting can affect HSYNC delay in the TVP70025I. Additionally, excessive filtering of HDTV and
graphics SOG sources can lead to sync attenuation and sync extraction issues.
CLP LPF SEL [1:0]: Coarse clamp low-pass filter selection. This filter affects the operation of all enabled coarse clamps which is generally
the SOG coarse clamp only.
00 = 4.8-MHz low-pass filter (default). Suitable for HDTV and graphics formats.
01 = 0.5-MHz low-pass filter. Suitable for SDTV formats.
10 = 1.7-MHz low-pass filter
11 = Reserved
CLK SEL: Clock reference select for Sync Processing block. The internal reference clock is typically 6.5 MHz, but it should not be
considered a precise clock. An external 27-MHz reference clock is therefore recommended for accurate mode detection. NOTE: The I2C
interface, Sync Separator, and activity detection circuitry always uses the internal clock reference.
0 = Internal clock reference (default)
1 = External clock reference (EXT_CLK)
NOTE: The external clock input also can be selected as the sample clock for the ADCs (see bit 1).
VS SEL: VSYNC input select
0 = VSYNC_A input selected (default)
1 = VSYNC_B input selected
PCLK SEL: Pixel clock selection. When the external clock input (pin 80) is selected as the ADC sample clock, the external clamp pulse
(pin 76) also should be selected (Bit 7 of subaddress 0Fh).
0 = ADC samples data using external clock input (pin 80)
1 = ADC samples data using H-PLL generated clock (default)
NOTE: The external clock input also can be selected as the reference clock for the Sync Processing block (see bit 3).
HS SEL: HSYNC input select
0 = HSYNC_A input selected (default)
1 = HSYNC_B input selected
NOTE: See the Sync Control register at subaddress 0Eh.
Copyright
2008–2011, Texas Instruments Incorporated
39
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