參數(shù)資料
型號： TVP70025IPZP
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： GREEN, PLASTIC, HTQFP-100
文件頁數(shù)： 47/59頁
文件大?。?/td> 519K
代理商： TVP70025IPZP
SLES232B
– JUNE 2008 – REVISED MAY 2011
AVID Start Pixel
Subaddress
40h
–41h
Default (012Ch)
Subaddress
7
6
5
4
3
2
1
0
40h
AVID start [7:0]
41h
Reserved
AVID active
AVID start [12:8]
AVID active
0 = AVID out active during VBLK (default)
1 = AVID out inactive during VBLK
AVID start [12:0]: AVID start pixel number, this is an absolute pixel location from the leading edge of HSYNC (start pixel 0). The TVP70025I
updates the AVID start only when the AVID start MSB byte is written to.
AVID start pixel register also controls the position of SAV code. The TVP70025I inserts the SAV code four pixels before the pixel number
specified in the AVID start pixel register.
AVID Stop Pixel
Subaddress
42h
–43h
Default (062Ch)
Subaddress
7
6
5
4
3
2
1
0
42h
AVID stop [7:0]
43h
Reserved
AVID stop [12:8]
AVID stop [12:0]: AVID stop pixel number. The number of pixels of active video must be an even number. This is an absolute pixel location
from the leading edge of HSYNC (start pixel 0).
The TVP70025I updates the AVID Stop only when the AVID Stop MSB byte is written to.
AVID stop pixel register also controls the position of EAV code.
VBLK Field 0 Start Line Offset
Subaddress
44h
Default (05h)
Subaddress
7
6
5
4
3
2
1
0
44h
VBLK start 0 [7:0]
VBLK start 0 [7:0]: VBLK start line offset for field 0 relative to the leading edge of VSYNC. The VBLK start line offset value affects the
location of transitions on the embedded sync V-bit and VBLK of the Data Enable output, but not the VSYNC output (VSOUT). The VSYNC
output simply follows the VSYNC input. Unsigned integer.
VBLK Field 1 Start Line Offset
Subaddress
45h
Default (05h)
Subaddress
7
6
5
4
3
2
1
0
45h
VBLK start 1 [7:0]
VBLK start 1 [7:0]: VBLK start line offset for field 1 relative to the leading edge of VSYNC. The VBLK start line offset value affects the
location of transitions on the embedded sync V-bit and VBLK of the Data Enable output, but not the VSYNC output (VSOUT). The VSYNC
output simply follows the VSYNC input. Unsigned integer.
VBLK Field 0 Duration
Subaddress
46h
Default (1Eh)
Subaddress
7
6
5
4
3
2
1
0
46h
VBLK duration 0 [7:0]
VBLK duration 0 [7:0]: VBLK duration in lines for field 0.
VBLK Field 1 Duration
Subaddress
47h
Default (1Eh)
Subaddress
7
6
5
4
3
2
1
0
47h
VBLK duration 1 [7:0]
VBLK duration 1 [7:0]: VBLK duration in lines for field 1.
Copyright
2008–2011, Texas Instruments Incorporated
51
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TVP70025IPZPR 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 Tr 8/10B,165/110MSPS Video ADC RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel
TVP7002EVM 功能描述:視頻 IC 開發(fā)工具 TVP7002 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Boards 類型:YPbPr to RGBHV Converters 工具用于評估:LMH1251 工作電源電壓:5 V
TVP7002PZP 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 Tr 8/10B 165/110MSPS Video ADC RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel
TVP7002PZPR 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 Tr 8/10B 165/110MSPS Video ADC RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel
TVP9000MZDSR 制造商:Texas Instruments 功能描述:
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