參數(shù)資料
型號: TVP70025IPZP
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: GREEN, PLASTIC, HTQFP-100
文件頁數(shù): 46/59頁
文件大小: 519K
代理商: TVP70025IPZP
SLES232B
– JUNE 2008 – REVISED MAY 2011
VSYNC Width
Subaddress
3Ch
Read only
7
6
5
4
3
2
1
0
Reserved
VSYNC width [4:0]
VSYNC width [4:0]: Number of lines between the leading and trailing edges of the VSYNC input. The VSYNC width along with the HSYNC
and VSYNC polarities can be used to determine whether the input graphics format is using VESA-CVT generated timings.
NOTE: The VSYNC width counter is not dependent on the H-PLL being locked.
Line Length Tolerance
Subaddress
3Dh
Default (03h)
7
6
5
4
3
2
1
0
Reserved
Line length tolerance [6:0]
Line length tolerance [6:0]: Controls sensitivity to HSYNC input stability when using either the internal or external clock reference. Increased
line length tolerance settings may be required for input signals having horizontal instability. This setting may affect the precision of the clock
cycles per line counter (see subaddresses 39h
–3Ah)
00h = (minimum) tolerance
03h = (default) tolerance
06h = (recommended) tolerance
7Fh = (maximum) tolerance
ADC Reference Setup
Subaddress
3Eh
Default (04h)
7
6
5
4
3
2
1
0
Reserved
Ref bias control [3:0]
Ref bias control [3:0]: Bias current control for ADC reference amplifier.
0h = Minimum setting
4h = Required (default)
Fh = Maximum setting
See bias current control for ADC at subaddress 2Ch.
Video Bandwidth Control
Subaddress
3Fh
Default (00h)
7
6
5
4
3
2
1
0
Reserved
BW select [3:0]
BW select [3:0]: Selectable low-pass filter settings for controlling the analog video bandwidth. This control affects the analog video
bandwidth of all three ADC channels.
0h = Highest video bandwidth (default)
Fh = Lowest video bandwidth (~90 MHz analog video bandwidth )
NOTE: This filter setting can be used to filter high frequency noise, but the filter lacks the precision for maximum filtering of s video formats.
The lowest bandwidth setting provides a video bandwidth of at least 50 MHz.
50
Copyright
2008–2011, Texas Instruments Incorporated
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