參數(shù)資料
型號(hào)： TVP70025IPZP
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： GREEN, PLASTIC, HTQFP-100
文件頁(yè)數(shù)： 9/59頁(yè)
文件大小： 519K
代理商： TVP70025IPZP
SLES232B
– JUNE 2008 – REVISED MAY 2011
Sync Processing
Horizontal Sync Selection
The TVP70025I provides two HSYNC inputs and three analog SOG inputs for HDTV and PC graphics inputs.
The sync input used by the horizontal PLL is automatically selected based on activity detection.
Sync Slicer
TVP70025I includes a circuit that compares the input signal on Green channel to a level 150 mV (typical value)
above the clamped level (sync tip). The slicing level is programmable by I2C register subaddress at 10h. The
digital output of the composite sync slicer is available on the SOGOUT pin.
Noise Immunity
In general, noise on a slowly varying input signal (i.e., sync falling edge) may cause a voltage comparator to
false trigger as the input passes through the linear range of the comparator. To improve the overall performance
of the TVP70025I sync slicer in the presence of noise on the SOG input, the voltage comparator includes
hysteresis. Maintaining a 50% slice level using the I2C programmable slice level control can further improve the
noise immunity of the Sync slicer. The slice level is programmable in 11.2-mV increments over a 350-mV range
as follows.
slice_level = (350 mV)
× (NTH/31)
where 0
≤ NTH ≤ 31, default: 11
0
≤ slice_level ≤ 350 mV
Glitch Immunity
During white-to-black transitions, the input video waveform may undershoot below the sync slicer threshold. To
help attenuate the amplitude of such glitches, a single-pole low-pass filter with three selectable cutoff frequencies
(2.5, 10, and 33 MHz) is provided at the input of the SOG voltage comparator circuit. This filter is bypassed in the
default mode.
NOTE
Although the low-pass filter may attenuate the amplitude of glitches present on the SOG
input, it also makes the sync falling edge less sharp.
Sync Separator
The sync separator automatically extracts VSYNC and HSYNC from the sliced composite sync input supplied at
the SOG input. The G or Y input containing the composite sync must be ac coupled to the SOG input pin using a
1-nF capacitor. Support for PC graphics, SDTV, EDTV, and HDTV is provided. The internal sync separator
provides support for formats having field rates (VSYNC frequencies) at or above 40 Hz. An external sync
separator or separated VSYNC must be used for field rates less than 40 Hz.
Sync Activity Detection
The TVP70025I provides activity detection on the sync inputs (VSYNC, HSYNC) to enable the host processor to
determine whether the PC graphics source is configured as a 3-wire, 4-wire, or 5-wire interface as defined here:
5 wire (G, B, R, HSYNC, VSYNC)
4 wire (G, B, R, CSYNC)
3 wire (G, B, R with SOG)
If activity is detected on the VSYNC input, the host processor should assume that the PC graphics input is a
standard 5-wire interface. In this case, the HSYNC input of the TVP70025I should be configured as an HSYNC
input. If AHSO and AVSO are set for automatic selection in I2C Reg 0Eh, the TVP70025I automatically uses the
HSYNC and VSYNC inputs, provided signals are present at both inputs.
Copyright
2008–2011, Texas Instruments Incorporated
17
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