參數(shù)資料
型號： TVP7002PZP
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： GREEN, PLASTIC, HTQFP-100
文件頁數(shù)： 20/57頁
文件大小： 517K
代理商： TVP7002PZP
SLES206B
– MAY 2007 – REVISED MAY 2011
Register Definitions
Chip Revision
Subaddress
00h
Read Only
7
6
5
4
3
2
1
0
Chip revision [7:0]
Chip revision [7:0]: Chip revision number
H-PLL Feedback Divider MSBs
Subaddress
01h
Default (67h)
7
6
5
4
3
2
1
0
PLL divide [11:4]
PLL divide [11:0]: Controls the 12-bit horizontal PLL feedback divider value that determines the number of pixels per line. PLL divide [11:4]
bits should be loaded first whenever a change is required.
H-PLL Feedback Divider LSBs
Subaddress
02h
Default (20h)
7
6
5
4
3
2
1
0
PLL divide [3:0]
Reserved
PLL divide [11:0]: Controls the 12-bit horizontal PLL feedback divider value that determines the number of pixels per line. PLL divide [11:4]
bits should be loaded first whenever a change is required.
H-PLL Control
Subaddress
03h
Default (A8h)
7
6
5
4
3
2
1
0
VCO [1:0]
Charge Pump Current [2:0]
Reserved
VCO [1:0]: Selects VCO frequency range
VCO Gain
VCO Range
Pixel Clock Frequency (PCLK)
(KVCO)
00 =
75
Ultra low
PCLK
< 36 MHz
01 =
85
Low
36 MHz
≤ PCLK < 70 MHz
10 =
150
Medium (default)
70 MHz
≤ PCLK < 135 MHz
11 =
200
High
135 MHz
≤ PCLK ≤ 165 MHz
Charge Pump Current [2:0]: Selects PLL charge pump current setting. The recommended charge pump current setting (ICP) can be
determined using the following equation.
ICP = 40 × KVCO/(pixels per line)
000 = 0: Small
101 = 5 (default)
111 = 7: Large
NOTE: Also see the PLL and CLAMP Control register at subaddress 0Fh.
Copyright
2007–2011, Texas Instruments Incorporated
27
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