參數(shù)資料
型號(hào)： TVP7002PZP
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： GREEN, PLASTIC, HTQFP-100
文件頁(yè)數(shù)： 26/57頁(yè)
文件大小： 517K
代理商： TVP7002PZP
SLES206B
– MAY 2007 – REVISED MAY 2011
Sync-On-Green Threshold
Subaddress
10h
Default (5Dh)
7
6
5
4
3
2
1
0
SOG Threshold [4:0]
Blue CS
Green CS
Red CS
SOG Threshold [4:0]: Sets the voltage level of the SOG slicer comparator according to the following equation.
slice_level = (350 mV)
× (NTH/31)
00h = 0 mV
0Bh = 124 mV (default)
1Fh = 350 mV
Blue Clamp Select: This bit has no effect when the Blue channel fine clamp is disabled (bit 2 of subaddress 2Ah).
0 = Bottom-level fine clamp
1 = Mid-level fine clamp (default)
Green Clamp Select: This bit has no effect when the Green channel fine clamp is disabled (bit 1 of subaddress 2Ah).
0 = Bottom-level fine clamp (default)
1 = Mid level fine clamp
Red Clamp Select: This bit has no effect when the Red channel fine clamp is disabled (bit 0 of subaddress 2Ah).
0 = Bottom-level fine clamp
1 = Mid-level fine clamp (default)
NOTE: Bottom-level clamping is required for Y and RGB inputs, while mid-level clamping is required for Pb and Pr inputs. The internal
clamp pulse must also be correctly positioned for proper clamp operation (see register 05h)
Sync Separator Threshold
Subaddress
11h
Default (20h)
7
6
5
4
3
2
1
0
Sync Separator Threshold [7:0]
Sync Separator Threshold [7:0]: Sets how many internal clock reference periods the sync separator counts to before toggling high or low.
Sync Separator Threshold [7:0]
× (minimum clock period) must be greater than the width of the negative sync pulse. This setting can also
affect the position of the VSOUT (see register 22h).
NOTE: The internal clock reference is typically 6.5 MHz, but a minimum clock period of 133 ns is recommended to allow for clock variation.
40h = recommended setting for support of most video formats
NOTE: Margin for a particular format can be maximized by using a mid-range setting below.
Format
MIN
MID
MAX
480i60Hz
1Fh
75h
ABh
480p60Hz
10h
64h
BAh
576i50Hz
20h
75h
ACh
576p50Hz
11h
64h
BCh
720p60Hz
1Bh
43h
6Ch
720p50Hz
37h
50h
6Ch
1080i60Hz
0Eh
2Ch
4Bh
1080i50Hz
21h
36h
4Bh
1080p60Hz
08h
2Dh
53h
1080p50Hz
1Bh
36h
53h
H-PLL Pre-Coast
Subaddress
12h
Default (00h)
7
6
5
4
3
2
1
0
Pre-Coast [7:0]
Pre-Coast [7:0]: Sets the number of HSYNC periods that coast becomes active prior to VSYNC leading edge. A minimum setting of 1 is
required to guarantee generation of an internal coast signal.
32
Copyright
2007–2011, Texas Instruments Incorporated
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