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| 型號： | TVP7002PZP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | GREEN, PLASTIC, HTQFP-100 |
| 文件頁數(shù)： | 34/57頁 |
| 文件大小： | 517K |
| 代理商： | TVP7002PZP |
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SLES206B
– MAY 2007 – REVISED MAY 2011
Table 1. Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Analog Video
RIN_1
11
I
Analog video input for R/Pr 1
RIN_2
10
I
Analog video input for R/Pr 2
RIN_3
9
I
Analog video input for R/Pr 3
GIN_1
2
I
Analog video input for G/Y 1
GIN_2
100
I
Analog video input for G/Y 2
GIN_3
98
I
Analog video input for G/Y 3
GIN_4
96
I
Analog video input for G/Y 4
BIN_1
18
I
Analog video input for B/Pb 1
BIN_2
17
I
Analog video input for B/Pb 2
BIN_3
16
I
Analog video input for B/Pb 3
The inputs must be ac coupled. The recommended coupling capacitor is 0.1
μF. Unused analog
inputs should be connected to ground using a 10-nF capacitor.
Clock Signals
DATACLK
28
O
Data clock output
EXT_CLK
80
I
External clock input. May be used as a timing reference for the mode detection block instead of
the internal clock reference. May also be used as the ADC sample clock instead of the H-PLL
generated clock.
Digital Video
R[9:0]
55
–59, 61–65
O
Digital video output of R/Cr, R[9] is the most significant bit (MSB).
G[9:0]
43-52
O
Digital video output of G/Y, G[9] is the MSB.
B[9:0]
29-38
O
Digital video output of B/Cb, B[9] is the MSB.
For 4:2:2 mode, multiplexed CbCr data is output on B[9:0].
Unused outputs can be left unconnected.
Miscellaneous Signals
PWDN
70
I
Power down input
0 = Normal mode
1 = Power down
RESETB
71
I
Reset input, active low. Outputs are placed in a high-impedance mode during reset (see
Table 11).
TMS
72
I
Test mode select input, active high. Used to enable scan test mode. For normal operation,
connect to ground.
FILT1
87
O
External filter connection for the horizontal PLL. A 0.1-
μF capacitor in series with a 1.5-k
resistor should be connected from this pin to pin 89 (see Figure 4).
FILT2
88
O
External filter connection for the horizontal PLL. A 4.7-nF capacitor should be connected from
this pin to pin 89 (see Figure 4).
PLL_F
89
I
Horizontal PLL filter internal supply connection
Host Interface
I2CA
73
I
I2C slave address input. The I2C slave address must be configured with an external pullup or
pulldown resistor (see Table 10).
0 = Slave address = B8h
1 = Slave address = BAh
SCL
74
I
I2C clock input
SDA
75
I/O
I2C data bus
4
Copyright
2007–2011, Texas Instruments Incorporated
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