參數(shù)資料
型號(hào): UCD9501
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processors
中文描述: 數(shù)字信號(hào)處理器
文件頁數(shù): 45/134頁
文件大?。?/td> 1133K
代理商: UCD9501
www.ti.com
3.6
System Control
PLL
X1
X2
Power
Modes
Control
Watchdog
Block
28x
CPU
P
Low-Speed Peripherals
SCI-A/B, SPI-A/B/C/D
Peripheral
Registers
High-Speed Prescaler
Low-Speed Prescaler
Clock Enables
GPIO
MUX
System
Control
Registers
XCLKIN
ADC
Registers
12-Bit ADC
16 ADC inputs
LSPCLK
I/O
Peripheral Reset
SYSCLKOUT
(A)
XRS
Reset
GPIOs
Peripheral
Registers
I/O
OSC
CLKIN
(A)
HSPCLK
eCAN-A/B
I
2
C-A
Peripheral
Registers
I/O
ePWM 1/2/3/4/5/6
eCAP 1/2/3/4 eQEP 1/2
Peripheral
Registers
CPU
Timers
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801 Digital Signal Processors
SPRS230G–OCTOBER 2003–REVISED FEBRUARY 2006
Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the
TMS320x280x System Control and Interrupts Reference
Guide
(literature number SPRU712).
This section describes the 280x oscillator, PLL and clocking mechanisms, the watchdog function and the
low power modes.
Figure 3-8
shows the various clock and reset domains in the 280x devices that will be
discussed.
A.
CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency
as SYSCLKOUT).
Figure 3-8. Clock and Reset Domains
Functional Overview
45
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