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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801 Digital Signal Processors
SPRS230G–OCTOBER 2003–REVISED FEBRUARY 2006
6-3
3.3-V Test Load Circuit
...........................................................................................................
97
Clock Timing
.......................................................................................................................
99
Power-on Reset
..................................................................................................................
100
Warm Reset
......................................................................................................................
101
Example of Effect of Writing Into PLLCR Register
..........................................................................
102
General-Purpose Output Timing
...............................................................................................
102
Sampling Mode
..................................................................................................................
103
General-Purpose Input Timing
.................................................................................................
104
IDLE Entry and Exit Timing
....................................................................................................
105
STANDBY Entry and Exit Timing Diagram
...................................................................................
106
HALT Wake-Up Using GPIOn
.................................................................................................
107
PWM Hi-Z Characteristics
......................................................................................................
108
ADCSOCAO or ADCSOCBO Timing
.........................................................................................
110
External Interrupt Timing
.......................................................................................................
110
SPI Master Mode External Timing (Clock Phase = 0)
......................................................................
113
SPI Master External Timing (Clock Phase = 1)
..............................................................................
115
SPI Slave Mode External Timing (Clock Phase = 0)
........................................................................
116
SPI Slave Mode External Timing (Clock Phase = 1)
........................................................................
117
ADC Power-Up Control Bit Timing
............................................................................................
119
ADC Analog Input Impedance Model
.........................................................................................
120
Sequential Sampling Mode (Single-Channel) Timing
.......................................................................
121
Simultaneous Sampling Mode Timing
........................................................................................
122
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
List of Figures
5