參數(shù)資料
型號： UCD9501
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 48/134頁
文件大小： 1133K
代理商： UCD9501
www.ti.com
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801 Digital Signal Processors
SPRS230G–OCTOBER 2003–REVISED FEBRUARY 2006
3.6.1.1
External Reference Oscillator Clock Option
The typical specifications for the external quartz crystal for a frequency of 20 MHz are listed below:
Fundamental mode, parallel resonant
C
L
(load capacitance) = 12 pF
C
L1
= C
L2
= 24 pF
C
shunt
= 6 pF
ESR range = 30 to 60
TI recommends that customers have the resonator/crystal vendor characterize the operation of their
device with the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank
circuit. The vendor can also advise the customer regarding the proper tank component values that will
produce proper start up and stability over the entire operating range.
3.6.1.2
PLL-Based Clock Module
The 280x devices have an on-chip, PLL-based clock module. This module provides all the necessary
clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio
control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before
writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which
takes 131072 OSCCLK cycles.
Table 3-15. PLLCR Register Bit Definitions
SYSCLKOUT
(CLKIN)
(2)
OSCCLK/2
OSCCLK
(OSCCLK*1)/2
(OSCCLK*2)/2
(OSCCLK*3)/2
(OSCCLK*4)/2
(OSCCLK*5)/2
(OSCCLK*6)/2
(OSCCLK*7)/2
(OSCCLK*8)/2
(OSCCLK*9)/2
(OSCCLK*10)/2
reserved
PLLCR[DIV]
(1)
PLLSTS[CLKINDIV]
0000 (PLL bypass)
0000 (PLL bypass)
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011-1111
0
1
0
0
0
0
0
0
0
0
0
0
0
(1)
(2)
This register is EALLOW protected.
CLKIN is the input clock to the CPU. SYSCLKOUT is the output
clock from the CPU. The frequency of SYSCLKOUT is the same as
CLKIN.
CAUTION
PLLSTS[CLKINDIV] can be set to 1 only if PLLCR is 0x0000. PLLCR should not be
changed once PLLSTS[CLKINDIV] is set.
The PLL-based clock module provides two modes of operation:
Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base
to the device.
External clock source operation - This mode allows the internal oscillator to be bypassed. The device
clocks are generated from an external clock source input on the X1 or the XCLKIN pin.
Functional Overview
48
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