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| 型號： | UDA1380TT |
| 元件分類： | 通用總線功能 |
| 英文描述： | Stereo audio coder-decoder for MD, CD and MP3 |
| 中文描述： | 立體聲音頻編碼器，可用于MD，CD和MP3解碼器 |
| 文件頁數(shù)： | 11/68頁 |
| 文件大小： | 278K |
| 代理商： | UDA1380TT |
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2002 Sep 16
11
Philips Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
8
FUNCTIONAL DESCRIPTION
8.1
Clock modes
There are two clock systems:
A SYSCLK signal, coming from the system or the SSA1
chip
A WSPLL which generates the internal clocks from the
incoming WSI signal.
The system frequency applied to pin SYSCLK is
selectable. The options are 256f
s
, 384f
s
, 512f
s
and 768f
s
.
Thesystemclockmustbelockedinfrequencytothedigital
interface signals.
Remark
: Since there is neither a fixed reference clock
available in the IC itself, nor a fixed clock available in the
systemtheICisin,thereisnoautosamplerateconversion
detection circuitry.
The system can run in several modes, using the two clock
systems:
Both the DAC and the ADC part can run at the applied
SYSCLK input. In this case the WSPLL is
powered-down
The ADC can run at the SYSCLK input, and at the same
time the DAC part can run (at a different frequency) at
the clock re-generated from the WSI signal
The ADC and the DAC can both run at the clock
regenerated from the WSI signal.
8.1.1
WSPLL
REQUIREMENTS
TheWSPLLismeanttolockontotheWSIinputsignal,and
regenerates a 256f
s
and 128f
s
signal for the FSDAC and
the interpolator core (and for the decimator if needed).
Since the operating range of the WSPLL is from
75 to 150 MHz, the complete range of 8 to 100 kHz
sampling frequency must be divided into smaller parts, as
given in Table 1, using Fig.4 as a reference. This means
that the user must set the input range of the WSI input
signal.
In case the SYSCLK is used for clocking the complete
system(decimatorincludinginterpolator)theWSPLLmust
be powered-down with bit ADC_CLK via the L3-bus
or I
2
C-bus.
The SEL_LOOP_DIV[1:0] can be controlled by the PLL1
and PLL0 bits in the L3-bus or I
2
C-bus register.
handbook, halfpage
VCO
DIV1
128fs
(digital parts)
256fs
(ADC and FSDAC)
PRE1
MGU527
Fig.4 WSPLL set-up.
Table 1
WSPLL divider settings
WORD SELECT
FREQUENCY (kHz)
SEL_LOOP_DIV[1:0]
PRE1
DIV1
VCO FREQUENCY
(MHz)
6.25 to 12.5
12.5 to 25
25 to 50
50 to 100
00
01
10
11
8
4
2
2
1536
1536
1536
768
76 to 153
相關PDF資料 |
PDF描述 |
|---|---|
| UDA1384 | Multichannel audio coder-decoder |
| UDA1384H | Multichannel audio coder-decoder |
| UDN2878W-2 | 10A SCRS |
| UDZ2.4B | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| UDZ10B | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| UDA1380TT/N2 | 制造商:PHILIP 功能描述: |
| UDA1380TT/N2,512 | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UDA1380TT/N2,518 | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UDA1380TT-T | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UDA1384 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multichannel audio coder-decoder |
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