- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382721 > UDA1380TT Stereo audio coder-decoder for MD, CD and MP3 PDF資料下載
參數(shù)資料
| 型號： | UDA1380TT |
| 元件分類： | 通用總線功能 |
| 英文描述： | Stereo audio coder-decoder for MD, CD and MP3 |
| 中文描述： | 立體聲音頻編碼器，可用于MD，CD和MP3解碼器 |
| 文件頁數(shù)： | 18/68頁 |
| 文件大?。?/td> | 278K |
| 代理商： | UDA1380TT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
2002 Sep 16
18
Philips Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
8.9
Application modes
The operation mode can be set with pin SEL_L3_IIC,
either to L3-bus mode (LOW) or to the I
2
C-bus mode
(HIGH) as given in Table 5.
For all features in microcontroller mode see Chapter 9.
Table 5
Pin function in the selected mode
Remark
: In the I
2
C-bus mode there is a bit A1 which sets
the LSB bit of the address of the UDA1380. In
L3-bus mode this bit is not available, meaning the device
has only one L3-bus device address.
8.10
Power-on reset
The UDA1380 has a dedicated pin RESET, which has a
pull-down resistor. This way a Power-on reset circuit can
be made with a capacitor and a resistor at the pin. The
internal pull-down resistor cannot be used because of the
5 V tolerant nature of the pad. The pull-down resistor is
shielded from the outside world by a transmission gate in
order to support 5 V tolerance.
The reset timing is determined by the external capacitor
and resistor which are connected to the pin RESET, and
the internal pull-down resistor. By the Power-on reset, all
the digital sound processing features and the system
controlling features are set to the default setting of the
L3-bus and I
2
C-bus control modes.
Remark
: The reset time should be at least 1
μ
s, and
during the reset time the system clock should be running.
In case the WSPLL is selected as the clock source, a clock
must be connected to the SYSCLK input in order to have
proper reset of the L3-bus or I
2
C-bus registers. This is
because by default the clock source is set to SYSCLK.
8.11
Power-down requirements
The following blocks have power-down control via the
L3-bus or I
2
C-bus interface:
Microphone amplifier (LNA) including its Single-Ended
to Differential Converter (SDC) and VGA
ADC plus SDC and the PGA, for left and right separate
Bias generation circuit for the front-end and the FSDAC
Headphone driver
WSPLL
FSDAC.
Clocksofthedecimator,interpolatorandtheanalogblocks
have separate enable and disable controls.
PIN
L3-BUS MODE
SEL_L3_IIC = L
I
2
C-BUS MODE
SEL_L3_IIC = H
L3CLOCK/SCL
L3MODE
L3DATA/SDA
L3CLOCK
L3MODE
L3DATA
SCL
A1
SDA
相關PDF資料 |
PDF描述 |
|---|---|
| UDA1384 | Multichannel audio coder-decoder |
| UDA1384H | Multichannel audio coder-decoder |
| UDN2878W-2 | 10A SCRS |
| UDZ2.4B | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| UDZ10B | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| UDA1380TT/N2 | 制造商:PHILIP 功能描述: |
| UDA1380TT/N2,512 | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UDA1380TT/N2,518 | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UDA1380TT-T | 功能描述:接口—CODEC SSA CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UDA1384 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multichannel audio coder-decoder |
發(fā)布緊急采購，3分鐘左右您將得到回復。