參數(shù)資料
型號(hào): UDA1380TT
元件分類: 通用總線功能
英文描述: Stereo audio coder-decoder for MD, CD and MP3
中文描述: 立體聲音頻編碼器,可用于MD,CD和MP3解碼器
文件頁數(shù): 39/68頁
文件大?。?/td> 278K
代理商: UDA1380TT
2002 Sep 16
39
Philips Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
11.8
Mode, bass boost and treble
Table 38
Register address 12H
Table 39
Description of register bits
Table 40
Flat/minimum/maximum setting bits
1
:
1
1
:
1
1
:
1
0
:
1
0
:
1
1
:
1
0
:
0
0
:
0
:
BIT
15
14
13
12
11
10
9
8
Symbol
Default
M1
0
M0
0
TRL1
0
TRL0
0
BBL3
0
BBL2
0
BBL1
0
BBL0
0
BIT
7
0
6
0
5
4
3
2
1
0
Symbol
Default
TRR1
0
TRR0
0
BBR3
0
BBR2
0
BBR1
0
BBR0
0
BIT
SYMBOL
DESCRIPTION
15 and 14
M[1:0]
Flat/minimum/maximum setting.
A 2-bit value to program the mode of the sound
processing filters of bass boost and treble. Default value 00, see Table 40.
Treble setting left.
A 2-bit value to program the mode of the sound processing filter of
treble. The used setting depends on the bits M1 and M0. Default value 00, see Table 41.
Bass boost setting left.
A 4-bit value to program the bass boost setting, which can be set
for left and right independently. The used set depends on the bits M1 and M0. Default
value 0000, see Table 42.
default value 00
Treble setting right.
A 2-bit value to program the mode of the sound processing filter of
treble. Default value 00, see Table 41.
Bass boost setting right.
A 4-bit value to program the bass boost setting, which can be
set for left and right independently. The used set depends on the mode bits. Default
value 0000, see Table 42.
13 and 12
TRL[1:0]
11 to 8
BBL[3:0]
7 and 6
5 and 4
TRR[1:0]
3 to 0
BBR[3:0]
M1
M0
MODE
0
0
1
1
0
1
0
1
flat (default)
minimum
minimum
maximum
VC2_7
VC1_7
VC2_6
VC1_6
VC2_5
VC1_5
VC2_4
VC1_4
VC2_3
VC1_3
VC2_2
VC1_2
VC2_1
VC1_1
VC2_0
VC1_0
VOLUME
(dB)
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