參數(shù)資料
型號(hào): UDA1380TT
元件分類: 通用總線功能
英文描述: Stereo audio coder-decoder for MD, CD and MP3
中文描述: 立體聲音頻編碼器,可用于MD,CD和MP3解碼器
文件頁(yè)數(shù): 45/68頁(yè)
文件大?。?/td> 278K
代理商: UDA1380TT
2002 Sep 16
45
Philips Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
Table 56
ADC input amplifier PGA gain setting bits
11.13 ADC settings
Table 57
Register address 22H
Table 58
Description of register bits
11 to 8
PGA_GAIN
CTRLR[3:0]
ADC input amplifier right gain settings.
A 4-bit value to program the gain of the input
amplifier. There are nine settings, for a gain range from 0 to 24 dB in steps of 3 dB. The
gain control of the PGA is independent for left and right. Default value 0000,
see Table 56.
default value 0
ADC input amplifier left gain settings.
A 4-bit value to program the gain of the input
amplifier. There are nine settings, for a gain range from 0 to 24 dB in steps of 3 dB. The
gain control of the PGA is independent for left and right. Default value 0000,
see Table 56.
7 to 4
3 to 0
PGA_GAIN
CTRLL[3:0]
PGA_GAINCTRLR3
PGA_GAINCTRLL3
PGA_GAINCTRLR2
PGA_GAINCTRLL2
PGA_GAINCTRLR1
PGA_GAINCTRLL1
PGA_GAINCTRLR0
PGA_GAINCTRLL0
PGA_GAIN (dB)
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
0 (default)
3
6
9
12
15
18
21
24
BIT
15
0
14
0
13
0
12
11
10
9
8
Symbol
Default
ADCPOL_ INV VGA_CTRL3 VGA_CTRL2
0
VGA_CTRL1
0
VGA_CTRL0
0
0
0
BIT
7
0
6
5
0
4
0
3
2
1
0
Symbol
Default
SEL_LNA
0
SEL_MIC
0
SKIP_DCFIL
1
EN_DCFIL
0
BIT
SYMBOL
DESCRIPTION
15 to 13
12
ADCPOL_INV
default value 000
ADC polarity control.
A 1-bit value to select ADC polarity. When this bit is logic 0:
polarity of ADC non-inverting. When this bit is logic 1: polarity of ADC inverting.
Default value 0.
Microphone input VGA gain settings.
A 4-bit value to program the gain of the LNA
in the microphone input channel. The range is 0 to 30 dB in steps of 2 dB.
Default value 0000, see Table 59.
11 to 8
VGA_CTRL[3:0]
BIT
SYMBOL
DESCRIPTION
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