
CHAPTER 6 EXCEPTION PROCESSING
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6.4.9 Cache Error Exception
Cause
The Cache Error exception occurs when a cache parity error is detected. This exception is not maskable, but
error detection can be disabled by setting the DE bit of the Status register.
If a parity error is detected when the DE bit of Status register is not set, a cache error exception is taken during
one of the following operations:
An instruction fetch from instruction cache
A load from the data cache
Tag parity check on a store
Main memory read by the processor
Most of the CACHE instructions (no exception is taken for the Index_Load_Tag and Index_Store_Tag
CACHE instructions)
In the V
R
4102, the parity error from the external bus and on-chip peripheral buses is not checked.
Processing
The processor sets the ERL bit in the Status register, saves the address to recover from the exception to the
ErrorEPC register, and then transfers to a special vector in uncached space.
If the BEV bit = 0, the vector is one of the following:
—
0xA000 0100 (virtual) in 32-bit mode
—
0xFFFF FFFF A000 0100 (virtual) in 64-bit mode
If the BEV bit = 1, the vector is one of the following:
—
0xBFC0 0300 (virtual) in 32-bit mode
—
0xFFFF FFFF BFC0 0300 (virtual) in 64-bit mode
Servicing
All errors should be logged. To correct cache parity errors, the system uses the CACHE instruction to invalidate
the cache block, overwrites the old data through a cache miss, and resumes execution with an ERET instruction.
Other errors are not correctable and are likely to be fatal to the current process.