
CHAPTER 15 PMU (POWER MANAGEMENT UNIT)
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(3) Activation via DCD Interrupt
When the DCD# signal is asserted, the PMU asserts the POWERON signal and provides external notification that
the CPU is being activated. After asserting the POWERON signal, the PMU checks the BATTINH/BATTINT# signal
and then de-asserts the POWERON signal.
If the BATTINH/BATTINT# signal is high (“1”), the PMU cancels peripheral unit reset, then starts the Cold Reset
sequence to activate the CPU core.
If the BATTINH/BATTINT# signal is low (“0”), the PMU sets “1” to PMUINTREG’s BATTINH bit and then performs
another shutdown. After the CPU is restarted, the BATTINH bit must be checked and cleared (to “0”) by software.
The PMUINTREG’s DCDST bit does not indicate whether a DCD interrupt has occurred but instead reflects the
current status of the DCD# pin.
Caution
While POWERON is active, the PMU cannot recognize changes in the DCD# signal. If the
DCD# state when POWERON is active is different from the DCD# state when POWERON is
inactive, the change in the DCD# signal is detected only after POWERON is inactive.
However, if the DCD# state when POWERON is active is the same as the DCD# state when
POWERON is inactive, any changes in the DCD# signal that occur while POWERON is active
are not detected.
Figure 15-5. Activation via DCD Interrupt (BATTINH/BATTINT# = 1)
BATTINH/
BATTINT#(i)
MPOWER(o)
POWERON(o)
DCD#(i)
RTC(Internal)
H
Figure 15-6. Activation via DCD Interrupt (BATTINH/BATTINT# = 0)
BATTINH/
BATTINT#(i)
MPOWER(o)
POWERON(o)
DCD#(i)
RTC(Internal)
L
L