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CHAPTER 14 ICU (INTERRUPT CONTROL UNIT)
This chapter describes the ICU register’s operations and settings.
14.1 GENERAL
The ICU collects interrupt signals from the various on-chip peripheral units and transfers these interrupt signals
(Int0, Int1, Int2, Int3, and NMI) to the CPU core.
The functions of the ICU’s internal blocks are briefly described below.
ADDECICU … Decodes read/write addresses from the CPU that are used for ICU registers.
REGICU …
This includes a register for interrupt masking. The initial value is “0”, which specifies masking.
No interrupt signal is supplied to CPU core unless the CPU writes “1” to this register.
OUTICU …
This is the general ICU output that follows masking of interrupts (all output is at the rising edge
of I_mclkin). It also controls the interrupt masking signal (doze_mskint) used for settings
during Suspend mode, assertion of the general interrupt source signal (int_all), and the
memdrv assertion timing signal (doze_memdrv) that is used when resetting from Suspend
mode.
The signals used to notice interrupt request to the CPU are as below.
NMI
: battint_intr only
Switching between NMI and Int0 is enabled according to this register’s settings.
Because NMI’s interrupt masking cannot be controlled by means of software, switch
to Int0 to mask battint_Intr.
Int3
: hsp_intr only
Int2
: rtc_long2_intr only
Int1
: rtc_long1_intr only
The IT (interval timer) and HSP interrupts require more responsiveness than do other
interrupt sources.
Int0
: All other interrupts
For details of the interrupt sources, see the register set.