參數(shù)資料
型號(hào)： UPD4564323G5-A10B-9JH
廠商： NEC Corp.
英文描述： 64M-bit Synchronous DRAM 4-bank, LVTTL
中文描述： 6400位同步DRAM 4銀行，LVTTL
文件頁數(shù)： 10/84頁
文件大小： 1048K
代理商： UPD4564323G5-A10B-9JH
Data Sheet M14376EJ2V0DS00
10
μ
PD4564323 for Rev.
E
Write command
(/CS, /CAS, /WE = Low, /RAS = High)
If the mode register is in the burst write mode, this command sets the burst
start address given by the column address to begin the burst write operation.
The first write data in burst mode can input with this command with
subsequent data on following clocks.
Fig.4
Column address and write
command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
(Bank select)
Col.
Read command
(/CS, /CAS = Low, /RAS, /WE = High)
Read data is available after /CAS latency requirements have been met.
This command sets the burst start address given by the column address.
Fig.5
Column address and read
command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
(Bank select)
Col.
CBR (auto) refresh command
(/CS, /RAS, /CAS = Low, /WE, CKE = High)
This command is a request to begin the CBR (auto) refresh operation. The
refresh address is generated internally.
Before executing CBR (auto) refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and ready for
a row activate command.
During t
RC
period (from refresh command to refresh or activate command),
the
μ
PD4564323 cannot accept any other command.
Fig.6
CBR (auto) refresh command
Add
A10
(Bank select)
/WE
/CAS
/RAS
/CS
CKE
CLK
H
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