
CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION
User
’
s Manual U15862EJ3V0UD
522
(a) Serial operation mode specification register n (CSIMAn)
This is an 8-bit register used to control the serial transfer operation.
This register can be set by an 8-bit or 1-bit memory manipulation instruction.
RESET input sets this register to 00H.
<7>
CSIAEn
Disable CSIAn operation (SOAn: Low level, SCKAn: High level)
Enable CSIAn operation
CSIAEn
0
1
CSIAn operation enable/disable control
CSIMAn
6
ATEn
5
ATMn
4
MASTERn
3
TXEn
2
RXEn
1
DIRn
0
0
1-byte transfer mode
Automatic transfer mode
ATEn
0
1
Automatic transfer operation enable/disable control
Single transfer mode (stops at address specified with ADTPn register)
Repeat transfer mode (Following transfer completion, the ADTCn register
is cleared to 00H and transmission starts again.)
ATMn
0
1
Specification of automatic transfer mode
Slave mode (synchronized with SCKAn input clock)
Master mode (synchronized with internal clock)
MASTERn
0
1
Specification of CSIAn master/slave mode
Disable transmission (SOAn: Low level)
Enable transmission
TXEn
0
1
Transmission enable/disable control
Disable reception
Enable reception
RXEn
0
1
Reception enable/disable control
MSB first
LSB first
DIRn
0
1
Specification of transfer data direction
After reset: 00H R/W Address: FFFFFD40H, FFFFD50H
When CSIAEn = 0, the CSIAn unit is reset asynchronously.
When CSIAEn = 0, the CSIAn unit is reset, so to operate CSIAn, first set CSIAEn = 1.
If the CSIAEn bit is changed from 1 to 0, all the registers of the CSIAn unit are
initialized. To set CSIAEn to 1 again, first re-set the registers of the CSIAn unit.
If the CSIAEn bit is changed from 1 to 0, the buffer RAM value is not held.
Also, when the CSIAEn bit is 0, the buffer RAM cannot be accessed.
When the TXEn bit is 0, read from the transfer buffer RAM is not possible.
When the RXEn bit is 0, write to the transfer buffer RAM is not possible.
Remark
n = 0 (V850ES/KF1)
n = 0, 1 (V850ES/KG1, V850ES/KJ1)