
User’s Manual U15862EJ3V0UD
755
APPENDIX B REVISION HISTORY
The following table shows the revision history up to this edition. The “Applied to:” column indicates the chapters of
each edition in which the revision was applied.
(1/3)
Edition
Major Revision from Previous Edition
Applied to:
Change of description in
Figure 12-1 Block Diagram of D/A Converter
CHAPTER 12 D/A
CONVERTER
Addition of
Caution
in
14.3.4 Interrupt control register (xxICn)
Addition of
Caution
in
14.3.6 In-service priority register (ISPR)
CHAPTER 14
INTERRUPT/EXCEPTION
PROCESSING FUNCTION
Addition of
CHAPTER 21 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
CHAPTER 21
ELECTRICAL
SPECIFICATIONS
(TARGET VALUES)
Addition of
CHAPTER 22 PACKAGE DRAWINGS
CHAPTER 22 PACKAGE
DRAWINGS
2nd
Addition of
APPENDIX A REGISTER INDEX
APPENDIX A REGISTER
INDEX
Addition of the following special quality grade products.
μ
PD703208(A), 703208Y(A), 703209(A), 703209Y(A), 703210(A), 703210Y(A),
703212(A), 703212Y(A), 703213(A), 703213Y(A), 703214(A), 703214Y(A), 703216(A),
703216Y(A), 703217(A), 703217Y(A), 70F3210(A), 70F3210Y(A), 70F3214(A),
70F3214Y(A), 70F3217(A), 70F3217Y(A)
Throughout
Addition of
Caution
in
1.2.4 Pin configuration (top view) (V850ES/KF1)
Addition of
Caution
in
1.3.4 Pin configuration (top view) (V850ES/KG1)
Addition of
Caution
in
1.4.4 Pin configuration (top view) (V850ES/KJ1)
CHAPTER 1
INTRODUCTION
Addition of description in
CHAPTER 2 PIN FUNCTIONS
and addition of
Table 2-1 Pin
I/O Buffer Power Supplies
Modification of description on recommended connection of P70 to P77, P78 to P715, IC,
V
PP
, and XT1 in
2.4 Pin I/O Circuits and Recommended Connection of Unused Pins
CHAPTER 2 PIN
FUNCTIONS
Modification of description in
3.4.8 (2) Access to special on-chip peripheral I/O
registers
CHAPTER 3 CPU
FUNCTIONS
Modification of description in
5.11 Bus Timing
Addition of
5.12
Cautions
CHAPTER 5 BUS
CONTROL FUNCTION
Addition of description on the main clock oscillator in
6.1 Overview
Addition of description in
6.2 (1) Main clock oscillator
Addition of
Caution 3
in
6.3 (1) Processor clock control register (PCC)
CHAPTER 6 CLOCK
GENERATION FUNCTION
Addition of description in
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05
Modification of description of
Caution 4
in
7.2 (2) 16-bit timer capture/compare
register 0n0 (CR0n0)
Modification of description of
Caution 4
in
7.2 (3) 16-bit timer capture/compare
register 0n1 (CR0n1)
Modification of description of
Caution 1
in
7.3 (3) 16-bit timer output control register
0n (TOC0n)
3rd
Addition of setting procedures and modification of description in
7.4.1 Operation as
interval timer (16 bits)
CHAPTER 7 16-BIT
TIMER/EVENT
COUNTERS 00 TO 05