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| 型號： | UPD72852A |
| 廠商： | NEC Corp. |
| 英文描述： | IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI |
| 中文描述： | 1個IEEE1394a 2000年的要求400 Mbps的雙端口PHY的大規(guī)模集成電路 |
| 文件頁數(shù)： | 11/48頁 |
| 文件大?。?/td> | 373K |
| 代理商： | UPD72852A |
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Data Sheet S16725EJ2V0DS
11
μ
PD72852A
Table
2-1. Bit Field Description (2/3)
Field
Size
R/W
Reset value
Description
Total_ports
4
R
0010
Supported port number.
0010: 2 ports
Max_speed
3
R
See
Description
Indicate the maximum speed that this node supports.
Set variable by SPD pin (61 pin).
When SPD = “0” then 001: 98.304 and 196.608 Mbps.
When SPD = “1” then 010: 98.304, 196.608 and 393.216 Mbps.
Delay
4
R
0000
Indicate worst case repeating delay time. 144 + (Delay
×
20) = 144 nsec
Link_active
1
R/W
1
Link active.
1: Enable
0: Disable
The logical AND status of this bit and LPS pin.
State will be referred to “L bit” of Self-ID Packet#0.
Contender
1
R/W
See
Description
Contender.
“1” indicate this node support bus manager function. This bit will be referred
to “C bit” of Self-ID Packet#0.
The reset data is depending on CMC pin setting.
CMC pin condition
1: Pull up (Contender)
0: Pull down (Non Contender)
Jitter
3
R
010
The difference of repeating time (Max.-Min.). (2+1)
×
20 = 60 nsec
Pwr_class
3
R/W
See
Description
Power class.
Please refer to IEEE1394a-2000 [4.3.4.1].
This bit will be referred to Pwr field of Self-ID Packet#0.
The reset data will be determined by PC0-PC2 Pin status.
Watchdog
1
R/W
0
Watchdog Enable.
This bit serves two purposes.
When set to 1, if any one port does resume, the Port_event bit becomes 1.
This function has no effect when SUS/RES (19 pin) = “0”.
To determine whether or not an interrupt condition shall be indicated to the
Link. On condition of LPS = 0 and Watchdog = 0, LKON as interrupt of Loop,
Pwr_fail, Timeout is not output. This function has effect both when SUS/RES
(19 pin) = “1” or “0”.
ISBR
1
R/W
0
Initiate short (arbitrated) bus reset.
Setting to 1 acquires the bus and begins short bus reset.
Short bus reset signal output : 1.3
μ
sec
Returns to 0 at the beginning of the bus reset.
Loop
1
R/W
0
Loop detection output.
1: Detection
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
Pwr_fail
1
R/W
1
Power cable disconnect detect.
It becomes 1 when there is a change from 1 to 0 in the CPS bit.
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
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