參數(shù)資料
型號(hào)： UPD72852A
廠商： NEC Corp.
英文描述： IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI
中文描述： 1個(gè)IEEE1394a 2000年的要求400 Mbps的雙端口PHY的大規(guī)模集成電路
文件頁(yè)數(shù)： 40/48頁(yè)
文件大?。?/td> 373K
代理商： UPD72852A
Data Sheet S16725EJ2V0DS
40
μ
PD72852A
DC Characteristics
Common
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Note 1
68
mA
Note 2
60
mA
Note 3
41
mA
Note 4
31
mA
Supply current
I
DD
Note 5
115
μ
A
Notes 1.
Transmit maximum packet (all ports transmitting maximum size isochronous packet - 4096 bytes, sent on
every isochronous interval, S400, data value of CCCCCCCCH), V
DD
= 3.3 V, T
A
= 25°C
2.
Repeat typical packet (receiving on one port DV packets on every isochronous interval, S100, and
transmitting on the other port), V
DD
= 3.3 V, T
A
= 25°C
3.
Idle (one port receiving and one port transmitting cycle starts), V
DD
= 3.3 V, T
A
= 25°C
4.
1 port receiving cycle start packet only, V
DD
= 3.3 V, T
A
= 25°C
5.
Suspend mode, V
DD
= 3.3 V, T
A
= 25°C
PHY/Link Interface
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
High-level output voltage
V
OH
CTL0, CTL1, D0-D7, LKON, SCLK,
I
OH
= –9 mA, V
DD
> 3 V
V
DD
–0.45
V
CTL0, CTL1, D0-D7, LKON, SCLK,
I
OH
= –4 mA, V
DD
= 2.7 V
V
DD
–0.4
V
Low-level output voltage
V
OL
CTL0, CTL1, D0-D7, LKON, SCLK,
I
OH
= +9 mA, V
DD
> 3 V
0.4
V
CTL0, CTL1, D0-D7, LKON, SCLK,
I
OH
= +4 mA, V
DD
= 2.7 V
0.4
V
High-level input voltage
V
IH
LPS, SPD, DIRECT, PC0-PC2, SUS/RES,
CMC
0.7V
DD
V
Low-level input voltage
V
IL
LPS, SPD, DIRECT, PC0-PC2, SUS/RES,
CMC
0.2V
DD
V
High-level input voltage (schmitt)
V
IHS
CTL0, CTL1, D0-D7, LREQ,
V
DD
> 3 V
0.456V
DD
+0.3
0.456V
DD
+0.9
V
Low-level input voltage (schmitt)
V
ILS
CTL0, CTL1, D0-D7, LREQ,
V
DD
> 3 V
0.456V
DD
–0.9
0.456V
DD
–0.3
V
High-level input current
I
IH
CTL0, CTL1, D0-D7,
V
I
= V
DD
, DIRECT = 0 V
–10
μ
A
LPS, SPD, DIRECT, PC0-PC2, SUS/RES,
CMC,
V
I
= V
DD
–10
μ
A
Low-level input current
I
IL
CTL0, CTL1, D0-D7, LKON, SCLK,
V
I
= 0 V, DIRECT = 0 V
10
μ
A
LPS, SPD, DIRECT, PC0-PC2, SUS/RES,
CMC,
V
I
= 0 V
10
μ
A
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