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參數(shù)資料
| 型號(hào)： | UPD75517 |
| 廠商： | NEC Corp. |
| 英文描述： | 4 BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁(yè)數(shù)： | 80/180頁(yè) |
| 文件大小： | 1596K |
| 代理商： | UPD75517 |
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80
μ
PD75517(A)
(4) Configuration and operation when the timer/pulse generator is used in the PWM pulse generation mode
Fig. 4-32 shows the configuration when the timer/pulse generator is used in the PWM pulse generation
mode.
The PWM pulse generation mode is selected by setting TPGM0 to 0. TPGM5 and TPGM7 are set to 1 to
enable pulse output. In the PWM mode, the PWM pulse signal can be output on the PPO pin, and IRQTPG
can be set at intervals of a fixed time period (2
15
/f
X
= 5.46 ms: at 6.0 MHz or 2
15
/f
X
= 7.81 ms: At 4.19 MHz).
PWM pulses output by the
μ
PD75517(A) are active-low and have an accuracy of 14 bits. This pulse signal
is applicable for electronic tuning and control of a DC motor when it is integrated by an external low-pass
filter and is converted to analog voltage. (See
Fig. 4-33
.)
The PWM pulse signal is generated by combining the basic period determined by 2
10
/f
X
and the secondary
period by 2
15
/f
X
so that the time constant of the external low-pass filter can be decreased.
Table 4-8 lists the basic and secondary periods by oscillator frequency.
Table 4-8 Basic and Secondary Periods
The low-level width of a PWM pulse depends on the 14-bit modulo latch value. The upper 8 bits of the
modulo latch are transferred from the 8 bits of MODH, and the lower 6 bits of the latch are transferred
from the upper 6 bits of MODL.
When the PWM pulse signal is converted to analog form, the voltage level of the analog output is obtained
as follows:
Value of modulo latch
2
14
V
AN
= V
ref
×
V
ref
: Reference voltage of external switching circuitry
To prevent an incorrect PWM pulse from being output by unstable modulo latch data being rewritten, the
μ
PD75517(A) allows correct data to be written in MODH and MODL beforehand with 8-bit manipulation
instructions, then in the 14-bit data which is to be transferred to the modulo latch at one time. This transfer
is referred to as reloading, and it is controlled by TPGM3. If TPGM3 is 0, reloading is disabled, and if it
is 1, reloading is enabled. Follow the procedure below to rewrite the modulo latch contents:
(i)
(ii)
(iii)
Clear TPGM3 to disable reloading.
Change the MODH and MODL contents.
Set TPGM3 to enable reloading.
Cautions 1.
If the modulo register H (MODH) is set to 0, the PWM pulse generator cannot function
normally. So be sure to set MODH to a value from 1 to 255.
If the lower 2 bits of the modulo register L (MODL) is read, the read result is unpredictable.
If the modulo latch is changed in a shorter period than the PWM pulse basic period
2
10
/f
X
(171
μ
s: at 6.0 MHz or 244
μ
s: at 4.19 MHz), PWM pulses do not change.
2.
3.
f
X
= 6.0 MHz
171
μ
s
5.46 ms
f
X
= 4.19 MHz
244
μ
s
7.81 ms
Basic period (2
10
/f
X
)
Secondary period (2
15
/f
X
)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD7554AG-597-E2 | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7554AG-597-E2-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7554AG-603-E2 | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7554AG-603-E2-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7554AG-611-E2 | 制造商:Renesas Electronics Corporation 功能描述: |
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