參數(shù)資料
型號： V58C365164S5
廠商： MOSEL-VITELIC
元件分類： DRAM
英文描述： 4M X 16 DDR DRAM, 0.1 ns, PDSO66
封裝： 0.400 INCH, PLASTIC, TSOP2-66
文件頁數(shù)： 23/44頁
文件大?。?/td> 507K
代理商： V58C365164S5
MOSEL VITELIC
V58C365164S
3
V58C365164S Rev. 1.5 November 2001
Capacitance*
TA =0to 70°C, VCC =3.3 V ± 0.2 V, f = 1 Mhz
*Note: Capacitance is sampled and not 100% tested.
Absolute Maximum Ratings*
Operating temperature range .................. 0 to 70 °C
Storage temperature range ................-55 to 150 °C
Input/output voltage.................. -0.3 to (VCC+0.3) V
Power supply voltage .......................... -0.3 to 4.6 V
Power dissipation ...........................................2.0 W
Data out current (short circuit).......................50 mA
*Note: Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Symbol
Parameter
Max. Unit
CI1
Input Capacitance (A0 to A11)
5
pF
CI2
Input Capacitance
RAS,CAS,WE,CS,CKE
5pF
CIO
Output Capacitance (DQ)
6.5
pF
CCLK
Input Capacitance (CCLK, CLK)4
pF
Block Diagram
Row decoder
Memory array
Bank 0
4096 x 256
x16bit
C
o
lu
mn
dec
oder
S
ens
e
a
mpl
ifi
er
&
I(
O
)
bus
Row decoder
Memory array
Bank 1
4096 x 256
x16 bit
C
o
lu
mn
d
e
c
o
der
S
e
ns
e
a
mpl
ifi
er
&
I(
O
)
bus
Row decoder
Memory array
Bank 2
4096 x 256
x16bit
Co
lu
m
n
d
e
c
o
d
e
r
S
ens
e
a
mpl
ifi
er
&
I(
O
)
bus
Row decoder
Memory array
Bank 3
4096 x 256
x16bit
Co
lu
m
n
d
e
c
o
d
e
r
S
ens
e
a
mpl
ifi
er
&
I(
O
)
bus
Input buffer
Output buffer
I/Q0-IQ15
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
A0 - A11, BA0, BA1
A0 - A7, AP, BA0, BA1
Control logic & timing generator
CL
K
CK
E
CS
RA
S
CA
S
WE
UDM
Row Addresses
Column Addresses
DLL
Strobe
Gen.
Data Strobe
CLK, CLK
CL
K
LD
M
DQS
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