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參數(shù)資料
| 型號(hào)： | VDP3130Y |
| 廠(chǎng)商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Video Processor Family |
| 中文描述： | 視頻處理器系列 |
| 文件頁(yè)數(shù)： | 26/76頁(yè) |
| 文件大?。?/td> | 1770K |
| 代理商： | VDP3130Y |
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VDP 313xY
ADVANCE INFORMATION
26
Micronas
2.12.Synchronization and Deflection
The synchronization and deflection processing is dis-
tributed over front-end and back-end. The video
clamping, horizontal and vertical sync separation and
all video related timing information are processed in
the front-end. Most of the processing that runs at the
horizontal frequency is programmed on the internal
Fast Processor (FP). Also the values for vertical and
East/West deflection are calculated by the FP soft-
ware.
The information extracted by the video sync process-
ing is multiplexed onto the hardware front sync signal
(FSY) and distributed internally to the rest of the video
processing system.
The data for the vertical deflection, the sawtooth and
the East/West correction signal is calculated in the
front end. The data is transferred to the back-end by a
single wire interface.
The display related synchronization, i.e. generation of
horizontal and vertical drive and synchronization of
horizontal and vertical drive to the video timing
extracted in the front-end, are implemented in hard-
ware in the back-end.
2.12.1. Deflection Processing
The deflection processing generates the signals for the
horizontal and vertical drive (see Fig. 2
–
24). This block
contains two phase-locked loops:
–
PLL2 generates the horizontal and vertical timing,
e.g. blanking, clamping and composite sync. Phase
and frequency are synchronized by the front sync
signal.
–
PLL3 adjusts the phase of the horizontal drive pulse
and compensates for the delay of the horizontal out-
put stage. Phase and frequency are synchronized
by the oscillator signal of PLL2.
The horizontal drive circuitry uses a digital sine wave
generator to produce the exact (subclock) timing for
the drive pulse. The generator runs at 1 MHz; in the
output stage the frequency is divided down to give
drive-pulse period and width. The horizontal drive
uses an open drain output transistor.
Fig. 2
–
24:
Deflection processing block diagram
phase
comparator
&
lowpass
PLL2
E/W
correction
sawtooth
PWM
15 bit
EW
VERT
VPROT
PWM
15 bit
DCO
front
sync
interface
FSY
VDATA
main
sync
generator
vertical
serial
data
phase
comparator
&
lowpass
PLL3
1:64
&
output
stage
HFLB
HOUT
DCO
display
timing
line
counter
blanking, clamping, etc.
clock & control
sinewave
generator
&
DAC
LPF
MSY
vertical reset
skew
measure-
ment
angle &
bow
+
VERTQ
sync
generation
CSY
VS
INTLC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VDP31XXB | Video Processor Family |
| VDP3108PR | Consumer IC |
| VDSGLD_38.88 | TRANS PREBIASED PNP 200MW SOT23 |
| VDSL5100I | TVS 400W 43V UNIDIRECT SMA |
| VDSL5100 | TVS 400W 40V BIDIRECT SMA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VDP3131Y | 制造商:MICRONAS 制造商全稱(chēng):MICRONAS 功能描述:Video Processor Family |
| VDP3132Y | 制造商:MICRONAS 制造商全稱(chēng):MICRONAS 功能描述:Video Processor Family |
| VDP3133Y | 制造商:MICRONAS 制造商全稱(chēng):MICRONAS 功能描述:Video Processor Family |
| VDP3134Y | 制造商:MICRONAS 制造商全稱(chēng):MICRONAS 功能描述:Video Processor Family |
| VDP313XY | 制造商:MICRONAS 制造商全稱(chēng):MICRONAS 功能描述:Video Processor Family |
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