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| 型號(hào)： | W229B |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 1/17頁 |
| 文件大小： | 183K |
| 代理商： | W229B |
Frequency Generator for Integrated Core Logic
with 133-MHz FSB
W229B
Cypress Semiconductor Corporation
Document #: 38-07223 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 21, 2002
408-943-2600
Features
Maximized EMI suppression using Cypress’s Spread
Spectrum technology
Low jitter and tightly controlled clock skew
Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
Two copies of CPU clock
Thirteen copies of SDRAM clock
Eight copies of PCI clock
One copy of synchronous APIC clock
Three copies of 66-MHz outputs
Two copies of 48-MHz outputs
One copy of selectable 24- or 48-MHz clock
One copy of double strength 14.31818-MHz reference
clock
Power-down control
SMBus interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter:................................................... 500 ps
CPU, 3V66 Output Skew: ........................................... 175 ps
SDRAM, APIC, 48-MHz Output Skew: ....................... 250 ps
PCI Output Skew: ....................................................... 500 ps
CPU to SDRAM Skew (@ 133 MHz) .......................
± 0.5 ns
CPU to SDRAM Skew (@ 100 MHz)................. 4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz)........................ 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead).......................... 1.5 to 3.5 ns
PCI to APIC Skew..................................................... ± 0.5 ns
Table 1. Frequency Selections
FS4 FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
CPU
75.3
95.0
129.0
150.0
150.0
110.0
140.0
144.0
68.3
105.0
138.0
140.0
66.8
100.2
133.6
133.6
157.3
160.0
146.6
122.0
127.0
122.0
117.0
114.0
80.0
78.0
166.0
133.6
66.6
100.0
133.3
133.3
SDRAM
113.0
95.0
129.0
113.0
150.0
110.0
140.0
108.0
102.5
105.0
138.0
105.0
100.2
100.2
133.6
100.2
118.0
120.0
110.0
91.5
127.0
122.0
117.0
114.0
120.0
117.0
124.5
133.6
100.0
100.0
133.3
100.0
3V66
75.3
63.3
86.0
75.3
75.0
73.0
70.0
72.0
68.3
70.0
69.0
70.0
66.8
66.8
66.8
66.8
78.6
80.0
73.3
61.0
84.6
81.3
78.0
76.0
80.0
78.0
83.0
89.0
66.6
66.6
66.6
66.6
PCI
37.6
31.6
43.0
37.6
37.5
36.6
35.0
36.0
34.1
35.0
34.5
35.0
33.4
33.4
33.4
33.4
39.3
40.0
36.6
30.5
42.3
40.6
39.0
38.0
40.0
39.0
41.5
44.5
33.3
33.3
33.3
33.3
APIC
18.8
15.8
21.5
18.8
18.7
18.3
17.5
18.0
17.0
17.5
17.0
17.5
16.7
16.7
16.7
16.7
19.6
20.0
18.3
15.2
21.1
20.3
19.5
19.0
20.0
19.5
20.7
22.2
16.6
16.6
16.6
16.6
SS
OFF
–
0.6%
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
±0.45%
±0.45%
±0.45%
±0.45%
OFF
OFF
OFF
–
0.6%
OFF
–
0.6%
OFF
OFF
OFF
OFF
OFF
OFF
–
0.6%
–
0.6%
–
0.6%
–
0.6%
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Block Diagram
Pin Configuration
Note:
1.
Internal pull-down or pull-up resistors present on inputs marked with
* or ^, respectively. Design should not rely solely on internal pull-up
or pull-down resistor to set I/O pins HIGH or LOW, respectively.
[1]
VDDQ3
VDDQ2
PCI1/FS1*
PCI2/FS2*
OSC
PLL REF FREQ
PLL 1
X2
X1
REF2X/FS3*
PCI3:7
48MHz_1/FS4*
SI0/24_48 MHz#*
PLL2
VDDQ3
I
2
C
Logic
SCLK
3V66_0:2
PCI0/FS0*
CPU0:1
APIC
Divider,
Delay,
and
Phase
Control
Logic
3
VDDQ3
2
SDRAM0:12
13
PWRDWN#
/2
(FS0:4*)
5
48MHz_0
REFVGX1
X2
VDDQ3
3V66_1
PCI0/GND
PCI1/FS1*
GND
VPCI4
PCI5
SI48M48MPCI7
W
VDDQ2
CPU1
SDRAM0
SDRAM2
GND
SDRAM4
SDRAM6
GND
^
SDRAM8
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SDATA
GND
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